Method and device for eliminating digital filter outputting DC component

Abstract

The invention relates to a method and device to eliminate the direct current component digital filter put out. The described method takes filter coefficients as a judgment, judge size of the contrary number of the sum coefficients and preset threshold quantity, determines the corresponding DC component eliminating model according to the judgment to eliminate the direct current component digital filter put out. The invention completely solve interference of direct current component the digital filter may introduce in, the implementation program is simple, consume fewer resources, implement with low cost. The filter will not generate direct current component no matter the input signal of the filter is normal input or temporarily closed.

Description

technical field [0001] The invention relates to the technical field of communication, in particular to a method and a device for eliminating a direct current component output by a digital filter. Background technique [0002] In the CDMA (Code Division Multiple Access) base station system, it is necessary to perform digital filtering on the baseband signal. long unit pulse response filter) filter, as shown in Figure 1. [0003] If the digital filter is not well designed, it is easy to generate a DC component. And even if the baseband input signal is turned off, that is, the input I / Q data is all zero, the signal output by the filter may still have a DC component. [0004] Usually IIR filters use DSP (Digital Signal Process, digital signal processor) devices or FPGA (Field Programmable Gate Array, field programmable gate array) logic devices to complete the filtering process; so how to use simple methods and use less circuits Resources to eliminate the DC component is the ...

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Problems solved by technology

[0009] The disadvantage of the above-mentioned prior art 1 is that although the filter does not generate a DC component output when there is a baseband signal input after the rounding process, for the IIR filter, if the signal input is suddenly closed during the filtering process, that is, the filter input When it is all zero, there may still be a DC component output

[0011] The disadvantage of the above-mentioned prior art 2 is that: real-time statistics of the input signal power need to consume more DSP or FPGA resources, the cost is high, and the statistics will bring delays, and the response speed is also slow

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