Dynamic load balancing

Abstract

A method and apparatus are provided for dynamically allocating access bandwidth to one or more resources to the threads of a multithreaded processor. This is done by providing an execution based metric for each thread and providing access to the resource in dependence on the execution based metrics of the threads. In addition, or alternatively, a resource based metric can be determined and access to the resource provided in dependence on the resource based metric.

Description

FIELD OF THE INVENTION [0001] This invention relates to a method and apparatus to dynamically allocate access bandwidth to one or more resources, such as memory to the threads of a multi-threaded microprocessor. In the case of memory access this improves memory latency, and in particular avoids overloading of an automatic MIPS allocation (AMA) control system in periods of intensive memory activity. BACKGROUND OF THE INVENTION [0002] Our British patent application no. 9607153.5 describes a multi-threaded processor and data processing management system in which a plurality of execution threads are routed between a plurality of data inputs and a plurality of data outputs via a data processing means. The data processing means has access to a data storage means. The system repeatedly determines which routing operations and which data processing operations are capable of being performed and commences execution of at least one of the routing or data processing operations on each clock cycl...

AI Technical Summary

Benefits of technology

[0008] Preferred embodiments of the present invention seek to optimise the memory latency in situations where more than one thread is requesting memory access. To achieve this, a register is used to store the page address of the last memory access accepted by the memory. For each access of each thread at the arbiter input the respective page addresses are calculated and compared with the page address held in the register storing the page address of the last memory access. This comparison can then be used to produce an in-page indication. In-page metrics of the various threads are then derived by multiplying the in-page indication with a user-defined weight, allowing user control over the in-page optimisation of memory accesses and between different threads. Note that memory with both open and close page policy could be optimised.

Problems solved by technology

However there are two main problems with such a scheme.

For example, if the memory is operating on the open page policy and the pre-arbiter chooses to send a memory access which is not in the same page as the last access, a high memory cycle latency will result due to amount of time needed to open a new page.

On the other hand, if the memory is operating on the close page policy, sending a memory request in the same page as the last would similarly result in a high latency.

This means it is possible that the operation of the AMA could be impeded.

In particular, in cases where there are periods of intense memory activity, the AMA control system could be overloaded simply due to the fact that the prearbiter 3 does not have any thread AMA information.

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