Method and apparatus for supporting verification, and computer product

Abstract

A verification supporting apparatus includes an acquiring unit that acquires a first verification-item list for a verification target, a functional specification of the verification target, and a sequential specification of the verification target; a keyword extracting unit that extracts a keyword about the verification target from the first verification-item list; a creating unit that creates a second verification-item list in which each of the verification items is formed with the functional description and the sequential description about an output action of the verification target; and a converting unit that converts the first verification-item list into a third verification-item list having a same format as the second verification-item list, based on the second verification-item list and the keyword.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS [0001] This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2004-381855, filed on Dec. 28, 2004, the entire contents of which are incorporated herein by reference. BACKGROUND OF THE INVENTION [0002] 1) Field of the Invention [0003] The present invention relates to a method and an apparatus for supporting verification in large-scale integration (LSI) design, and a computer product. [0004] 2) Description of the Related Art [0005] In LSI design, improvement of work efficiency by shortening a design period has conventionally been demanded. However, in the LSI design, a verification process, which is rather time consuming, to verify whether an LSI properly operates is essential. Especially for an LSI that is required to be large-scale, to have high performance, to be high-speed, and to be low-power consuming, the verification process is important to maintain high quality. [0006] In the ver...

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Benefits of technology

[0013] It is an object of the present invention to solve a

Problems solved by technology

However, in the LSI design, a verification process, which is rather time consuming, to verify whether an LSI properly operates is essential.

Moreover, a technology for objectively evaluating necessity and sufficiency of the verification items in the verification item list has not been established.

Therefore, in some cases, necessary verification items are missed to be extracted, or unnecessary verification items are undesirably extracted.

In addition, this reduces a yield in actual manufacturing of the LSI.

Moreover, because the review requires 3 to 10 people or more to be involved as review members, schedule arrangement itself can be a trouble for a coordinator, taking time and labor.

In addition, if the schedule arrangement does not proceed smoothly, a reviewing period becomes long.

Thus, a total time required for the LSI design increases.

Furthermore, the review usually requires about two hours to half a day.

This not only makes the verification period long, but also causes a delay in other processes in the LSI design because of binding hours constraints for the members.

Therefore, the verification process requires a great deal of time and labor.

This makes the design period long, and increases manufacturing cost.

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