Hardware support for superpage coalescing

Abstract

A method of assigning virtual memory to physical memory in a data processing system allocates a set of contiguous physical memory pages for a new page mapping, instructs the memory controller to move the virtual memory pages according to the new page mapping, and then allows access to the virtual memory pages using the new page mapping while the memory controller is still copying the virtual memory pages to the set of physical memory pages. The memory controller can use a mapping table which temporarily stores entries of the old and new page addresses, and releases the entries as copying for each entry is completed. The translation look aside buffer (TLB) entries in the processor cores are updated for the new page addresses prior to completion of copying of the memory pages by the memory controller. The invention can be extended to non-uniform memory array (NUMA) systems. For systems with cache memory, any cache entry which is affected by the page move can be updated by modifying its address tag according to the new page mapping. This tag modification may be limited to cache entries in a dirty coherency state. The cache can further relocate a cache entry based on a changed congruence class for any modified address tag.

Description

BACKGROUND OF THE INVENTION [0001] 1. Field of the Invention [0002] The present invention generally relates to computer systems, specifically to memory subsystems for computers, and more particularly to a method of providing efficient mappings between virtual memory and physical memory. [0003] 2. Description of the Related Art [0004] The basic structure of a conventional computer system 10 is shown in FIG. 1. Computer system 10 may have one or more processing units, two of which 12a and 12b are depicted, which are connected to various peripheral devices, including input / output (I / O) devices 14 (such as a display monitor, keyboard, and permanent storage device), memory device 16 (such as random access memory or RAM) that is used by the processing units to carry out program instructions, and firmware 18 whose primary purpose is to seek out and load an operating system from one of the peripherals (usually the permanent memory device) whenever the computer is first turned on. Processing...

AI Technical Summary

Benefits of technology

"The present invention provides an improved method for coalescing superpages in a data processing system. The method reduces latencies associated with page copying and facilitates efficient coalescing. It also includes a hardware-supported method for migrating virtual-to-physical memory mappings in a memory hierarchy including cache levels. The invention allows for efficient use of virtual memory while reducing the impact on cache entries. Overall, the invention improves performance and efficiency in data processing."

Problems solved by technology

However, if the data in the chosen block is not modified, the block is simply abandoned and not written to the next lowest level in the hierarchy.

However, the use of superpages gives rise to a tradeoff.

While superpages can improve the TLB hit rate by reducing the number of entries that need to be concurrently maintained in the TLB, they can also lead to underutilization of the physical memory if the application does not use the entire superpage.

This approach, however, still has drawbacks.

During this time, the application continues to suffer from poor TLB behavior.

Secondly, the size of the memory controller page tables limits the availability of remapped superpages, and the mapping table can quickly grow.

These limitations are exacerbated in NUMA systems having multiple memory controllers.

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