Disabling portions of memory with non-deterministic errors

Abstract

Systems and methods are disclosed herein for identifying and avoiding attempts to access a defective portion of memory. Various techniques are provided for detecting a defect in a portion of memory and dynamically avoiding future attempts to access the defective portion of memory. More specifically, the techniques detect and avoid both hard and erratic errors.

Description

BACKGROUND OF THE INVENTION[0001]Data storage, referred to generically herein as “memory,” is commonly implemented in computer systems. Computer systems may employ a multi-level hierarchy of memory, with relatively fast, expensive but limited-capacity memory at the lowest level of the hierarchy and proceeding to relatively slower, lower cost but higher-capacity memory at the highest level of the hierarchy. The hierarchy may include a fast memory called a cache, either physically integrated within a processor or mounted physically close to the processor for speed. In addition, the computer system may use multiple levels of caches.[0002]From time-to-time a defect may occur within a portion of memory. Such defect may occur and be detected during manufacturing (or “fabricating”) the memory, or such defect may be a latent defect that is not observed until after the memory chip has been supplied by the manufacturer. Latent defects may be caused, for example, by aging, stresses, and / or act...

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Such defect may occur and be detected during manufacturing (or “fabricating”) the memory, or such defect may be a latent defect that is not observed until after the memory chip has been supplied by the manufacturer.

Latent defects may be caused, for example, by aging, stresses, and/or actual use of the memory, which results in errors from the point of view of the memory.

Thus, latent defects refer to defects that were not present (or did not manifest themselves) during the testing and production of the...

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