Single datapath floating point implementation of RCP, SQRT, EXP and LOG functions and a low latency RCP based on the same techniques

a floating point, single datapath technology, applied in the field of computer systems, can solve problems such as large gate counts

Inactive Publication Date: 2013-04-11
VIVANTE CORPORATION
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The hardware implementation of such large data look up tables results in large gate counts proportional to the size of the data look up tables.

Method used

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  • Single datapath floating point implementation of RCP, SQRT, EXP and LOG functions and a low latency RCP based on the same techniques
  • Single datapath floating point implementation of RCP, SQRT, EXP and LOG functions and a low latency RCP based on the same techniques
  • Single datapath floating point implementation of RCP, SQRT, EXP and LOG functions and a low latency RCP based on the same techniques

Examples

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Embodiment Construction

[0022]FIG. 1 is a block diagram illustrating a 6 stage unified hardware pipeline according to an embodiment of the present invention. Here, block 101, block 103, block 105, block 107, block 109, block 111, and block 113 are the register stages of the pipeline. Block 102 is a floating point to fixed point converter. Block 112 is a fixed point to floating point converter. In an example, block 112 may be configured to be bypassing circuit according to an opcode (i.e., a configuration instruction, a micro-code, or the like) for implementing an EXP function. In another example block 102 may be configured to be bypassing circuit according to another opcode (i.e., a configuration instruction, a micro-code, or the like) for implementing an LOG function. In still other examples, both block 102 and block 112 may be configured to be bypassing circuits according to yet another opcode (i.e., a configuration instruction, a micro-code, or the like) in implementing RCP or SQRT functions. In some ex...

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Abstract

Methods and apparatus is provided for computing mathematical functions comprising a single pipeline for performing a polynomial approximation (e.g. a quadratic polynomial approximation, or the like); and one or more data tables corresponding to at least one of the RCP, SQRT, EXP or LOG functions operable to be coupled to the single pipeline according to one or more opcodes; wherein the single pipeline is operable for computing at least one of RCP, SQRT, EXP or LOG functions according to the one or more opcodes.

Description

BACKGROUND INFORMATIONRelated Applications[0001]1. Field of the Invention[0002]The invention related generally to the field of computer systems and more particularly to computational functions for graphics processor chips.[0003]2. Description of Related Art[0004]Graphics processor chips traditionally employ various mathematical functions implemented in hardware for fast drawing and rendering speed. Some examples of these mathematical functions include reciprocal function (“RCP”), reciprocal square root function (“SQRT”), exponential function (“EXP”) and logarithmic function (“LOG”). These mathematical functions are implemented in prior art as separate circuitry blocks with different algorithms.[0005]For example, in a three cycle RCP implementation in the prior art, a floating point number x may be represented as a concatenation of a most significant bits (“MSB”) portion x0 and a least significant bits (“LSB”) portion x1 where x1=x−x0. The main calculation for reciprocal of x is in t...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): G06F7/60
CPCG06F1/0356G06F7/5525G06F7/556G06F7/60G06F2101/10G06F2101/12G06F2101/08G06F17/10
Inventor CAI, MIKE M.ZHONG, LEFAN
Owner VIVANTE CORPORATION
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