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Semiconductor packaging method and structure thereof

Active Publication Date: 2013-08-22
CHIPBOND TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

The present invention provides a semiconductor packaging method that includes using a conductive gel with anti-dissociation function to prevent short circuits caused by copper ions. This method involves mounting a chip on a substrate with pads, forming a conductive gel with anti-dissociation function on the pads, and connecting the chip's copper bumps to the pads' conductive areas through the conductive particles in the gel. The anti-dissociation substances in the gel capture any dissociated copper ions, preventing them from causing short circuits. This ensures the stability and reliability of the semiconductor packaging.

Problems solved by technology

However, a short phenomenon is easily occurred in mentioned circuit layout via an insufficient gap between two adjacent electronic connection devices.

Method used

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  • Semiconductor packaging method and structure thereof
  • Semiconductor packaging method and structure thereof
  • Semiconductor packaging method and structure thereof

Examples

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Embodiment Construction

[0005]With reference to FIGS. 1A to 1C, a semiconductor packaging method in accordance with a preferred embodiment of the present invention includes the steps as followed. First, referring to FIG. 1A, providing a substrate 110 having an upper surface 111 and a plurality of pads 112 disposed at the upper surface 111, in this embodiment, the pad 112 can be a pin of the substrate 110 or a bump pad of trace lines. Each of the pads 112 comprises a first coupling surface 113 and a lateral surface 114, wherein the first coupling surface 113 comprises a plurality of first conductive contact areas 113a and a plurality of first non-conductive contact areas 113b. Next, referring to FIG. 1B, FIG. 1B indicates forming a conductible gel with anti-dissociation function 120 on the upper surface 111 and the pads 112 of the substrate 110, wherein the conductible gel with anti-dissociation function 120 includes a plurality of conductive particles 121 and a plurality of anti-dissociation substances 122...

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PUM

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Abstract

A semiconductor packaging method includes providing a substrate having a plurality of pads, each of the pads comprises a first coupling surface having a plurality of first conductive contact areas and a plurality of first non-conductive contact areas; forming a conductible gel with anti-dissociation function on the substrate, said conductible gel includes a plurality of conductive particles and a plurality of anti-dissociation substances; mounting a chip on the substrate, said chip comprises a plurality of copper-containing bumps, each of the copper-containing bumps comprises a ring surface and a second coupling surface having a plurality of second conductive contact areas and a plurality of second non-conductive contact areas, wherein the conductive particles are electrically connected with the first conductive contact areas and the second conductive contact areas, said anti-dissociation substances are in contact with the second non-conductive contact area, and the ring surfaces are covered with the anti-dissociation substances.

Description

FIELD OF THE INVENTION[0001]The present invention is generally related to a semiconductor packaging method, which particularly relates to the semiconductor packaging method that prevents copper ions from dissociation.BACKGROUND OF THE INVENTION[0002]Modern electronic products gradually lead a direction of light, thin, short, and small. Accordingly, the circuit layout for electronic products destines to develop technique such as “micro space between two electronic connection devices”. However, a short phenomenon is easily occurred in mentioned circuit layout via an insufficient gap between two adjacent electronic connection devices.SUMMARY[0003]The primary object of the present invention is to provide a semiconductor packaging method includes providing a substrate having an upper surface and a plurality of pads disposed at the upper surface, and each of the pads comprises a first coupling surface having a plurality of first conductive contact areas and a plurality of first non-conduc...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): H01L23/488H01L21/60
CPCH01L21/50H01L24/81H01L2224/9211H01L2224/81903H01L2224/81191H01L24/29H01L2224/16225H01L2224/32225H01L2224/73204H01L2224/83192H01L24/13H01L24/16H01L24/32H01L2224/83851H01L24/83H01L24/92H01L2224/13144H01L2224/13147H01L2224/13155H01L2224/2929H01L2224/293H01L2224/29393H01L2224/29499H01L2924/00012H01L2924/00014H01L2224/81H01L2224/83H01L2924/00
Inventor SHIH, CHENG-HUNGLIN, SHU-CHENLIN, CHENG-FANHSIEH, YUNG-WEIJIANG, BO-SHIUN
Owner CHIPBOND TECH