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Reference current generation in resistive memory device

Active Publication Date: 2015-12-10
INTEGRATED SILICON SOLUTION
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, due to limitations in the fabrication process, the resistance values for the high and low resistance levels are often distributed over a range.

Method used

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  • Reference current generation in resistive memory device
  • Reference current generation in resistive memory device
  • Reference current generation in resistive memory device

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Embodiment Construction

[0013]The invention can be implemented in numerous ways, including as a process; an apparatus; a system; and / or a composition of matter. In this specification, these implementations, or any other form that the invention may take, may be referred to as techniques. In general, the order of the steps of disclosed processes may be altered within the scope of the invention.

[0014]A detailed description of one or more embodiments of the invention is provided below along with accompanying figures that illustrate the principles of the invention. The invention is described in connection with such embodiments, but the invention is not limited to any embodiment. The scope of the invention is limited only by the claims and the invention encompasses numerous alternatives, modifications and equivalents. Numerous specific details are set forth in the following description in order to provide a thorough understanding of the invention. These details are provided for the purpose of example and the inv...

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Abstract

A resistive memory device incorporates a reference current generation circuit to generate a reference current for the sense amplifier that is immune to variation in the resistance of the reference resistive memory cells. In some embodiments, the reference current generation circuit uses reference resistive memory cells configured in the low resistance state only. The reference current generation circuit generates the reference current by combining a reference cell current and a bias current. The bias current is regulated by a feedback circuit in response to changes in the reference current to maintain the reference current at a substantially constant value and having a current value being an average of the cell currents for a resistive memory cell in the high resistance state and the low resistance state.

Description

BACKGROUND OF THE INVENTION[0001]Resistive random-access memory (RRAM or “resistive memory”) is a type of non-volatile memory where the data storage function is implemented in a variable resistance element whose resistance value can change between a low level and a high level. For example, most resistive memory devices include as the variable resistance element a controllable resistor material between upper and lower conductive electrodes. The controllable resistor material may be a transition metal oxide or other suitable materials. A conductive path is created or dissolved in the controllable resistor material, corresponding to low-resistive and high-resistive states. A resistive memory cell in a resistive memory device typically includes a variable-resistance resistive memory element connected serially with a switching device acting as a cell selector. The switching device is typically an NMOS transistor.[0002]In some examples, a resistive memory cell can store a logical “0” valu...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): G11C13/00
CPCG11C13/004G11C13/0038G11C7/14G11C11/1673G11C13/0002G11C2013/0054
Inventor PARK, GEUN-YOUNGJANG, SEONG JUNKIM, JUSTIN
Owner INTEGRATED SILICON SOLUTION