Via formation using sidewall image transfer process to define lateral dimension

Abstract

A method of forming a via to an underlying layer of a semiconductor device is provided. The method may include forming a pillar over the underlying layer using a sidewall image transfer process. A dielectric layer is formed over the pillar and the underlying layer; and a via mask patterned over the dielectric layer, the via mask having a mask opening at least partially overlapping the pillar. A via opening is etched in the dielectric layer using the via mask, the mask opening defining a first lateral dimension of the via opening in a first direction and the pillar defining a second lateral dimension of the via opening in a second direction different than the first direction. The via opening is filled with a conductor to form the via. A semiconductor device and via structure are also provided.

Description

BACKGROUND[0001]1. Technical Field[0002]The present disclosure relates to semiconductor processing, and more specifically, to a method of forming a fully self-aligned via using a sidewall image transfer process to define a lateral dimension of the via.[0003]2. Related Art[0004]In the microelectronics industry as well as in other industries involving construction of microscopic structures (e.g., micromachines, magnetoresistive heads, etc.) there is a continued desire to reduce the size of structural features and microelectronic devices and / or to provide a greater amount of circuitry for a given chip size. Miniaturization in general allows for increased performance (more processing per clock cycle and less heat generated) at lower power levels and lower cost. Present technology is at atomic level scaling of certain micro-devices such as logic gates, FETs and capacitors, for example. Circuit chips with hundreds of millions of such devices are common.[0005]Sidewall image transfer (SIT),...

AI Technical Summary

Problems solved by technology

One challenge in making interconnects of semiconductor devices in ever-smaller circuit chips is that it is difficult to control the via's width relative to an intended critical dimension (CD).

The above problem of improper via dimensioning during fabrication may be caused by a number of self-aligned via processing characteristics.

First and foremost, the critical dimension control in the different directions is not maintained outside of the hard mask.

In addition, the aspect ratio control of the self-aligned via may also not be controlled leading to improper dimensions.

These approaches suffer from a number of drawbacks such as the need for additional masking layers increasing the overlay placement, the need for more precise etching bias control and tuning to control the hard mask critical dimension, and finally, the lack of control of the via placement on the lower interconnect level.

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