Nonvolatile semiconductor memory device and method of manufacturing the same
a semiconductor memory and non-volatile technology, applied in the direction of semiconductor devices, electrical devices, transistors, etc., can solve the problems of metal contamination, short circuit between each element,
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first embodiment
Overall Configuration
[0015]FIG. 1 is a block diagram of a nonvolatile semiconductor memory device according to a first embodiment. This nonvolatile semiconductor memory device includes a memory cell array 101 that has a plurality of memory cells MC disposed substantially in a matrix therein and that comprises a bit line BL and a word line WL disposed orthogonally to each other and connected to these memory cells MC. Provided in a periphery of this memory cell array 101 are a column control circuit 102 and a row control circuit 103. The column control circuit 102 controls the bit line BL and performs data erase of the memory cell, data write to the memory cell, and data read from the memory cell. The row control circuit 103 selects the word line WL and applies a voltage for data erase of the memory cell, data write to the memory cell, and data read from the memory cell.
[0016]A data input / output buffer 104 is connected to an external host 109, via an I / O line, and receives write data,...
second embodiment
[0060]Next, a nonvolatile semiconductor memory device according to a second embodiment will be described with reference to FIGS. 20 and 21. An overall configuration of the nonvolatile semiconductor memory device of this second embodiment has a circuit configuration and a planar layout of the memory cell array 101 which are identical to those of the first embodiment (FIGS. 1 to 3), hence duplicated descriptions thereof will be omitted. However, a cross-sectional structure of the memory cell is different from that of the first embodiment. Moreover, FIG. 20 is a cross-sectional view taken along the line I-I′ of FIG. 3 and FIG. 21 is a cross-sectional view taken along the line II-II′ of FIG. 3, of the nonvolatile semiconductor memory device according to the second embodiment. In FIGS. 20 and 21, configurations identical to those of the first embodiment are assigned with identical reference symbols to those assigned in FIGS. 4 and 5, and duplicated descriptions thereof will be omitted be...
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