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Three dimensional integrated circuit structure and manufacturing method of the same

Active Publication Date: 2017-03-02
TAIWAN SEMICON MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

The patent text describes a method for manufacturing a three-dimensional integrated circuit (3DIC) that involves stacking semiconductor dies on top of each other. The method includes steps to prepare the semiconductor dies, such as forming a device and metallization structure, and to stack the dies on top of each other. The 3DIC offers improved integration density and faster speeds compared to traditional packaging techniques. The patent text also describes the use of a three-dimensional packaging technique called three-dimensional interconnect (3DI) that allows for the integration of multiple semiconductor dies in a package. The technical effects of the patent text include improved integration density, faster speeds, and better performance of the 3DIC.

Problems solved by technology

However, there are many challenges related to 3DICs.

Method used

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  • Three dimensional integrated circuit structure and manufacturing method of the same
  • Three dimensional integrated circuit structure and manufacturing method of the same
  • Three dimensional integrated circuit structure and manufacturing method of the same

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Embodiment Construction

[0006]The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a second feature over or on a first feature in the description that follows may include embodiments in which the second and first features are formed in direct contact, and may also include embodiments in which additional features may be formed between the second and first features, such that the second and first features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations discussed.

[0007]F...

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Abstract

Three dimensional integrated circuit structures and manufacturing methods of the same are disclosed. The three dimensional integrated circuit structure includes a first chip and a second chip. The first chip is bonded to the second chip at a bonding interface. A through via of the first chip and a bonding pad of the second chip are electrically connected, and a diffusion barrier layer of the through via contacts the bonding pad at the bonding interface.

Description

BACKGROUND[0001]The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continual reductions in minimum feature size. This allows more components to be integrated into a given area. In some applications, these smaller electronic components also require smaller packages that utilize less area than conventional packages.[0002]Three dimensional integrated circuits (3DICs) are a recent development in semiconductor packaging in which multiple semiconductor dies are stacked upon one another, such as package-on-package (PoP) and system-in-package (SiP) packaging techniques. Some 3DICs are prepared by placing dies over dies on a semiconductor wafer level. The 3DICs have, for example, decreased length of interconnects between the stacked dies, and thus provide improved integration density and other advantages, such as faster speeds and higher bandwidth. However, there are many challen...

Claims

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Application Information

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IPC IPC(8): H01L25/07H01L25/00H01L23/538
CPCH01L25/074H01L25/50H01L23/5386H01L23/5384H01L21/76898H01L23/481H01L25/0657H01L2224/11H01L2225/06541H01L2225/06544H01L21/48H01L23/522
Inventor CHENG, KUANG-WEICHEN, YI-HSIUYANG, KU-FENGCHIOU, WEN-CHIH
Owner TAIWAN SEMICON MFG CO LTD