Memory device including ovonic threshold switch adjusting threshold voltage thereof

Abstract

A memory device may include a substrate, a first conductive line on the substrate and extending in a first direction, a second conductive line over the first conductive line and extending in a second direction crossing the first direction, a third conductive line over the second conductive line and extending in the first direction, a first memory cell at an intersection of the first conductive line and the second conductive line and including a first selection element layer and a first variable resistance layer, and a second memory cell at an intersection of the second conductive line and the third conductive line and including a second selection element layer and a second variable resistance layer. A first height of the first selection element layer in a third direction perpendicular to the first and second directions is different than a second height of the second selection element layer in the third direction.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS[0001]This application claims priority under 35 U.S.C. §119 to Korean Patent Application No. 10-2016-0020680, filed on Feb. 22, 2016, and Korean Patent Application No. 10-2016-0050113, filed on Apr. 25, 2016 in the Korean Intellectual Property Office, the disclosures of which are incorporated herein in their entirety by reference.BACKGROUND[0002]Technical Field[0003]Embodiments of the present disclosure relate to memory devices. More specifically, embodiments of the present disclosure relate to memory devices having a cross-point structure.[0004]Description of Related Art[0005]The integration of semiconductor memory devices has been increased as sizes of the electronic devices have been reduced. Thus, three-dimensional cross-point memory devices which include a plurality of memory cells disposed at intersection points of two electrodes crossing each other have been studied to be scaled down. However, in the down-scaling process, since thickness...

AI Technical Summary

Benefits of technology

The patent describes a memory device that includes a substrate, multiple conductive lines, and memory cells. The first conductive lines run parallel to the top surface of the substrate and are spaced apart in one direction, while the second conductive lines run parallel to the first lines in the same direction. The third conductive lines run parallel to the second lines in the opposite direction. The memory cells are located at the intersection of the first and second lines and the second and third lines, with each cell including a selection element layer and a variable resistance layer. The thickness of the selection element layer is greater in one direction than in another direction. The patent also describes how the memory device can include a first word line layer and a common bit line layer, with a first memory cell layer and a second memory cell layer between them. The thickness of the variable resistance layers and the ovonic threshold switching layers in the memory cells can be different. The technical effect of this invention is to provide a memory device with improved performance and reliability.

Problems solved by technology

However, in the down-scaling process, since thicknesses of layers used to form the three-dimensional cross-point array memory devices also are reduced, the layers exposed to high temperature processes can be easily damaged and degraded.

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