Hybrid metal interconnects with a bamboo grain microstructure

Abstract

A method of forming an interconnect with a bamboo grain microstructure. The method includes forming a conductive filler layer in a trench of an insulating layer to a predetermined depth such that an aspect ratio of a top portion of the trench is reduced to a threshold level, depositing a metal layer over the conductive filler layer in the top portion of the trench, the metal layer having a plurality of small grains, and annealing the metal layer to provide a bamboo grain microstructure having larger grains than grain boundaries of the plurality of small grains.

Description

BACKGROUND[0001]Technical Field[0002]The present invention relates to semiconductor devices and, more particularly, to forming hybrid metal interconnects with a bamboo grain microstructure for semiconductor devices.[0003]Description of the Related Art[0004]Existing semiconductor devices often employ interconnects and / or contacts formed from a single material in a single layer. However, as device dimensions continue to decrease due to evolving technology, high aspect ratios of narrow features in the device, such as patterned features including interconnects and / or contacts, tend to increase. In addition, small grain structure within the narrow features persists due to the increased aspect ratios, especially toward the bottom of such narrow features even after annealing processes. These small grain microstructures in interconnect lines may significantly reduce electromigration performance of the semiconductor device.[0005]Reducing the initial depth of the narrow features to lower the ...

AI Technical Summary

Problems solved by technology

These small grain microstructures in interconnect lines may significantly reduce electromigration performance of the semiconductor device.

Assuming a fixed linewidth constraint, however, means that having a shorter line decreases the volume of copper and thus increases electrical resistance.

In addition, barrier layers embedded in the interconnect lines may sacrifice resistivity of the device, and high temperature annealing processes may affect via chain yield.

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