Control chip for memory power sequence

Abstract

A control chip for memory power sequence including input pins, a control circuit and output pins is provided. The control chip is compatible with a plurality of processor platforms. The input pins are configured to receive control signals corresponding to each of the processor platforms. The control circuit is configured to determine a selected processor platform among the processor platforms in which the control chip for memory power sequence is operated, and generate corresponding power switching signals according to the control signals of the selected processor platform. The output pins are configured to output the corresponding power switching signals to control a power sequence of a memory on the selected processor platform.

Description

CROSS-REFERENCE TO RELATED APPLICATION[0001]This application claims the priority benefit of Taiwan application serial no. 105211307, filed on Jul. 27, 2016. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.BACKGROUND OF THE DISCLOSURE1. Field of the Disclosure[0002]The present disclosure relates to a control chip, and more particularly, to a control chip for memory power sequence and compatible with a plurality of processor platforms.2. Description of Related Art[0003]In general, different processor platforms (e.g., an Intel processor platform or an AMD processor platform) have different requirements in a power sequence of a dynamic random access memory (DRAM) installed thereon.[0004]For instance, power-supply sources required by a double-data-rate fourth generation synchronous dynamic random access memory (DDR4 SDRAM) circuit include a VPP power source (2.5 V), a VDD power source (or a VDDQ power...

AI Technical Summary

Benefits of technology

[0006]In view of the foregoing, the present disclosure provides a control chip for memory power sequence and compatible with a plurality of processor platforms, so that a development time may be reduced for the circuit designers and complexity and costs of material preparation are also reduced.

[0010]Based on the above, the control chip for memory power sequence proposed by the present disclosure is compatible with multiple processor platforms. That is to say, the control chip for memory power sequence proposed by the embodiments of the present disclosure can provide a complete solution to the power sequence of the memory circuit for different processor platforms. As a result, the development time may be reduced for the circuit designers while also reducing the complexity and costs of material preparation for the different processor platforms.

Problems solved by technology

For this reason, the designers are bounded to prepare different circuit components (e.g., the specific logic chip and the discrete circuit as described above) for the different processor platforms, and increases on the complexity and the costs for material preparation are unavoidable.

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