Virtual Ground Non-volatile Memory Array

Abstract

A memory device with memory cell pairs each having a single continuous channel region, first and second floating gates over first and second portions of the channel region, an erase gate over a third portion of the channel region between the first and second channel region portions, and first and second control gates over the first and second floating gates. For each of the pairs of memory cells, the first region is electrically connected to the second region of an adjacent pair of memory cells in the same active region, and the second region is electrically connected to the first region of an adjacent pair of the memory cells in the same active region.

Description

RELATED APPLICATIONS[0001]This application is a continuation of U.S. application Ser. No. 14 / 935,201, which claims the benefit of U.S. Provisional Application No. 62 / 078,873, filed Nov. 12, 2014, and which are incorporated herein by reference.FIELD OF THE INVENTION[0002]The present invention relates to non-volatile memory arrays.BACKGROUND OF THE INVENTION[0003]Split gate non-volatile flash memory cells are well known. For example, U.S. Pat. No. 6,747,310 discloses such memory cells having source and drain regions defining a channel region there between, a select gate over one portion of the channel regions, a floating gate over the other portion of the channel region, and an erase gate over the source region. The memory cells are formed in pairs that share a common source region and common erase gate, with each memory cell having its own channel region in the substrate extending between the source and drain regions (i.e. there are two separate channel regions for each pair of memor...

AI Technical Summary

Benefits of technology

The patent describes a memory device that includes a substrate with isolation regions and active regions between them. The active regions have a different conductivity type than the substrate and a continuous channel region between them. The device also includes a floating gate, a control gate, and erase gates. The memory cells are arranged in an array and connected in a specific way to allow for efficient memory operations. The technical effects of this design include improved memory cell performance and reliability, as well as efficient and reliable memory operations.

Problems solved by technology

Given the number of electrodes for each cell (source, drain, select gate, control gate and erase gate), and two separate channel regions for each pair of memory calls, configuring and forming the architecture and array layout with all the various lines connected to these electrodes can be overly complex and difficult to implement, especially as critical dimensions continue to shrink.

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