Process for controlling the read amplifiers of a memory and corresponding memory integrated circuit

Abstract

An integrated circuit includes a memory, and the memory includes a memory plane arranged in rows and columns, and a plurality of read amplifiers connected to the columns of the memory plane. A reference path includes first and second reference columns, and a reference memory cell is connected between the first and second reference columns. A reference row is connected to the reference memory cell for selection thereof so that the first reference column conducts a discharge current and the second reference column conducts a leakage current. A control circuit is connected between the first and second reference columns and the read amplifiers. The control circuit provides an activation signal to the read amplifiers when an absolute value of a difference between voltages on the first and second reference columns exceeds a threshold.

Description

FIELD OF THE INVENTION[0001]The invention relates to integrated circuits, especially memory circuits, and more particularly, taking into account the leakage currents of the bit lines when controlling the read amplifiers connected to the columns of a memory.[0002]The invention applies advantageously but not limitingly to adjusting the timing in delivering signals for monitoring a memory on the integrated circuit. In particular, the memory may be a static random access memory (SRAM) or a dynamic random access memory (DRAM). The memory may also be an embedded memory, that is, a memory embodied jointly with other components through the same technological process, and integrated within an application specific integrated circuit (ASIC).BACKGROUND OF THE INVENTION[0003]Conventionally, when the memory cells of a memory plane of a memory are connected in a differential mode between two bit lines one of the bit lines, during a read operation and after having been precharged to a high voltage,...

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Problems solved by technology

However, in reality, this other bit line is also drawn to ground on account of leakage currents from the other memory cells connected to this other bit line.

A worst-case situation may be, for example, a very high temperature for which the leakage currents are significant.

However, such an approach, if it leads to an acceptable performance in the worst-case situation, limits the performance of the memory in intermediate and normal operating situations.

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