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Method of testing a multichip

a multi-chip and test method technology, applied in the field of multi-chips, can solve the problems of limited test pattern, timing, load, resistance, etc., and achieve the effect of reducing the number of tests

Inactive Publication Date: 2009-12-08
SAMSUNG ELECTRONICS CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

Enables comprehensive package-level testing of multichips, allowing for various test patterns to be generated and applied, thereby identifying and addressing defects at the interface between chips, improving reliability and functionality.

Problems solved by technology

However, even though each of the selected single chips is acceptable, defects relating to timing, load, and resistance may occur at an interface between the chips as a result of the stacking process.
However, a package level test is not performed on a typical multichip after the stack process.
Additionally, a test pattern is also limited while testing a single chip.

Method used

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  • Method of testing a multichip

Examples

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Embodiment Construction

[0051]Illustrative embodiments of the present invention will be described below in more detail with reference to the accompanying drawings. The present invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this description will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. While describing these embodiments, detailed descriptions of well-known items, functions, or configurations are typically omitted for conciseness.

[0052]The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a,”“an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,”“comprising,”“includes” and / or...

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Abstract

A multichip and method of testing a multichip, the multichip including a control chip having a central processing unit (CPU) and a plurality of memories, each memory of the plurality of memories storing information related to testing the multichip, comprises connecting one of the memories to the control chip; reading, by the CPU, stored memory information from the connected one of the memories to confirm the connected one of the memories; generating a test pattern relating to the connected one of the memories confirmed by the CPU, and testing the connected one of the memories according to the test pattern.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS[0001]This U.S. non-provisional patent application claims priority under 35 U.S.C. § 119 of Korean Patent Application No. 10-2006-0112371, filed in the Korean Intellectual Property Office on Nov. 14, 2006, the entire contents of which are hereby incorporated by reference in their entirety.BACKGROUND OF THE INVENTION[0002]1. Field of the Invention[0003]The present invention described herein relates to a multichip, and more particularly, to a multichip capable of testing a memory and a method of testing the multichip.[0004]2. Description of the Related Art[0005]System-in-Package (SiP), Multichip Package (MCP), and Package-on-Package (POP) technologies are widely used to achieve low power consumption and miniaturization of electronic application products such as the latest portable smart phones, personal digital assistants (PDAs), navigation devices, etc.[0006]FIG. 1 is a block diagram of a SiP 10 in embodiments of a multichip. Referring to FIG. 1...

Claims

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Application Information

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Patent Type & Authority Patents(United States)
IPC IPC(8): G01R31/28
CPCG11C5/02G11C29/08G11C5/04H01L2924/15311H01L25/18G06F11/28
Inventor JUNG, JIN-KOOK
Owner SAMSUNG ELECTRONICS CO LTD