Method for processing semiconductor substrate and method for manufacturing semiconductor device in which said processing method is used

a technology of semiconductor substrate and processing method, which is applied in the direction of semiconductor devices, semiconductor/solid-state device details, electrical devices, etc., can solve the problems of contaminating surrounding areas, unable to separate the si semiconductor substrate and the supporting plate from one another, and the method is limited to temperatures less than or equal, so as to improve the mechanical strength prevent the cracking of the semiconductor substrate, and improve the adhesion

Active Publication Date: 2017-10-03
FUJI ELECTRIC CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

This method enhances the mechanical strength of semiconductor substrates, prevents cracking, and allows for high-temperature processing without substrate contamination, improving manufacturing efficiency and yield by using a vacuum and laser separation technique with a suitable wavelength for the substrate materials.

Problems solved by technology

However, if an adhesive with low heat resistance such as a wax or a polymer-based adhesive is used to bond together the semiconductor substrate and the supporting plate and the assembly is heated to a temperature greater than the heat resistance temperature of the adhesive during the manufacturing method, voids may form in the bonded region and cause the substrates to separate, the adhesive may melt and contaminate the surrounding areas, or the chemical properties of the adhesive may change and make it impossible to separate the Si semiconductor substrate and the supporting plate apart from one another.
This type of method suffers from being limited to temperatures less than or equal to the heat resistance temperature of the adhesive (100° C. to 400° C.) during all processes that occur after the semiconductor substrate bonding process.
However, SiC substrates are excellent thermal conductors, therefore making it difficult to perform the necessary heat treatments while keeping the temperature of the adhesive portions of the SiC substrate less than or equal to the heat resistance temperature of the polymer-based adhesive used.
Moreover, when manufacturing reverse-blocking IGBT devices, the applied layer of the polymer-based adhesive may be exposed to acids, alkalis, gases, plasmas, or the like via through-portions formed during through-etching on the rear surface of the Si substrate.
This exposure may cause issues or defects in the adhesive.

Method used

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  • Method for processing semiconductor substrate and method for manufacturing semiconductor device in which said processing method is used
  • Method for processing semiconductor substrate and method for manufacturing semiconductor device in which said processing method is used
  • Method for processing semiconductor substrate and method for manufacturing semiconductor device in which said processing method is used

Examples

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embodiment 1

[0063]Next, a method of processing a semiconductor substrate according to Embodiment 1 that includes bonding together an SiC substrate and a supporting plate and separating apart the SiC substrate and the supporting plate, as well as a method of manufacturing a MOSFET according to Embodiment 1 in which the processing method is used will be described in detail with reference to FIGS. 1A to 1I.

[0064]An n-type 4H-SiC crystal (it is preferable that a 4H or 6H polytype be used for manufacturing a device) with a diameter of 3 inches, a thickness of 350 μm, and an impurity concentration of 1×1018 cm−3 is used for an SiC substrate 1. The front surface of the SiC substrate 1 is planarized to a surface roughness Ra1) with an impurity concentration of 1×1016 cm−3 and a thickness of 10 μm is deposited on the front surface of the planarized SiC substrate. Next, as illustrated in FIG. 1A, a first device process is performed to form a MOS transistor that includes a gate electrode, a p-type channel...

embodiment 2

[0075]Next, a method of processing a semiconductor substrate according to Embodiment 2 that includes bonding together an SiC substrate and a supporting plate and separating apart the SiC substrate and the supporting plate, as well as a method of manufacturing a MOSFET according to Embodiment 2 in which the processing method is used will be described with reference to FIGS. 2A to 2I.

[0076]In Embodiment 2, the first device process for forming the MOSFET in the SiC substrate 1 is the same as in Embodiment 1 (here, FIG. 2A corresponds to the step illustrated in FIG. 1B). Next, the facing surfaces 2 of the SiC substrate 1 in which the MOSFET is formed and the SiC supporting plate 4 are irradiated with the ion beam 5 in a vacuum and gas-etched to activate those surfaces. As in Embodiment 1, a 200 W Ar ion beam is used.

[0077]Next, as illustrated in FIG. 2B, amorphous Si layers 6 (with a thickness of 20 nm) are formed as films on the ion beam 5-irradiated surfaces of the SiC supporting plat...

embodiment 3

[0080]Next, a method of processing a semiconductor substrate according to Embodiment 3 that includes bonding together an SiC substrate and a supporting plate and separating apart the SiC substrate and the supporting plate, as well as a method of manufacturing a MOSFET according to Embodiment 3 in which the processing method is used will be described with reference to FIGS. 3A to 3I.

[0081]In Embodiment 2 as described above, the bonding layer 8a includes not only the amorphous Si layers 6 but also the metal layer 7 (the Ni metal layer 7). However, in the method of manufacturing a semiconductor device described in Embodiment 2, the Ni metal layer 7 was formed on only one of the facing surfaces of the SiC substrate 1 in which the MOSFET is formed and the supporting plate 4. As illustrated in FIGS. 3A to 3I, in Embodiment 3 the method of manufacturing a semiconductor devices includes forming a triple-layer amorphous Si layer 6 / Ni metal layer 7 / amorphous Si layer 6 stack on both of the fa...

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Abstract

Provided are a method of processing a semiconductor substrate and a method of manufacturing a semiconductor device that uses this method of processing. The method of processing the semiconductor substrate includes: a bonding step in which a supporting plate, which is composed primarily of a material that substantially transmits laser light of prescribed wavelength, and a principal surface of a semiconductor substrate, which is composed primarily of a material that substantially transmits the laser light of the prescribed wavelength, are arranged to face each other in a vacuum and then pressed together in the vacuum with an intermediate layer that includes an amorphous silicon layer interposed therebetween; and a separating step in which, after the laser light is radiated from a side of the supporting plate and the intermediate layer absorbs laser energy, the semiconductor substrate and the supporting plate are separated from each other.

Description

BACKGROUND OF THE INVENTION[0001]Technical Field[0002]The present invention relates to a method of processing a semiconductor substrate that includes bonding a supporting plate to a semiconductor substrate and separating the bonded supporting plate from the semiconductor substrate, as well as to a method of manufacturing a semiconductor device in which the processing method is used.[0003]Background Art[0004]Vertical power devices include a plurality of layers formed by diffusing or implanting impurities into a semiconductor substrate. Of these layers, the drift layer (the layer along which carriers drift due to the electric field) tends to exhibit a higher electrical resistance than the other layers. Forming this drift layer too thickly results in a significant increase in the on-voltage and the forward voltage drop of the device, which tends to cause an undesirable increase in the normal operation loss of the device. Therefore, there is demand to reduce the thickness of the drift l...

Claims

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Application Information

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Patent Type & AuthorityPatents(United States)
IPC IPC(8): H01L21/48H01L21/02H01L21/324H01L21/683H01L29/16H01L29/20H01L21/28H01L23/00
CPCH01L21/4871H01L21/0245H01L21/02505H01L21/28H01L21/324H01L21/6835H01L29/1608H01L29/2003H01L23/562H01L2221/6834H01L2221/68327H01L2221/68381H01L21/045H01L21/0485H01L21/2007H01L29/66068H01L29/045
InventorIGUCHI, KENICHI
OwnerFUJI ELECTRIC CO LTD