51 results about "Multigate device" patented technology

Self-aligned gate cutting techniques are disclosed herein that provide dielectric gate isolation fins for isolating gates of multigate devices from one another. An exemplary device includes a first multigate device having first source / drain features and a first metal gate that surrounds a first channel layer and a second multigate device having second source / drain features and a second metal gate that surrounds a second channel layer. A dielectric gate isolation fin separates the first metal gate from the second metal gate. The dielectric gate isolation fin includes a first dielectric layer having a first dielectric constant and a second dielectric layer having a second dielectric constant disposed over the first dielectric layer. The second dielectric constant is greater than the first dielectric constant. The first metal gate and the second metal gate physically contact the first channel layer and the second channel layer, respectively, and the dielectric gate isolation fin.

Source / drain silicide that improves performance and methods for fabricating such are disclosed herein. An exemplary device includes a first channel layer disposed over a substrate, a second channel layer disposed over the first channel layer, and a gate stack that surrounds the first channel layer and the second channel layer. A source / drain feature disposed adjacent the first channel layer, second channel layer, and gate stack. The source / drain feature is disposed over first facets of the first channel layer and second facets of the second channel layer. The first facets and the second facets have a (111) crystallographic orientation. An inner spacer disposed between the gate stack and the source / drain feature and between the first channel layer and the second channel layer. A silicide feature is disposed over the source / drain feature where the silicide feature extends into the source / drain feature towards the substrate to a depth of the first channel layer.

Semiconductor devices having improved source / drain features and methods for fabricating such are disclosed herein. An exemplary device includes a semiconductor layer stack disposed over a mesa structure of a substrate. The device further includes a metal gate disposed over the semiconductor layer stack and an inner spacer disposed on the mesa structure of the substrate. The device further includes a first epitaxial source / drain feature and a second epitaxial source / drain feature where the semiconductor layer stack is disposed between the first epitaxial source / drain feature and the second epitaxial source / drain feature. The device further includes a void disposed between the inner spacer and the first epitaxial source / drain feature.

An exemplary gate stack includes a gate dielectric (e.g., a high-k dielectric layer over an interfacial layer) and a gate electrode (e.g., a work function layer over the high-k dielectric layer, a cap over the work function layer, and a bulk fill layer over the cap). The gate stack wraps and / or surrounds a first semiconductor layer disposed over a second semiconductor layer. The gate dielectric and the work function layer (and not the cap and / or the bulk fill layer) fill a space between the first semiconductor layer and the second semiconductor layer. A ratio of oxygen in outer portions of the gate stack to inner portions of the gate stack may be about 1 to about 1.25. A thickness of the work function layer at inner portions of the gate stack may be less than a thickness of the work function layer at outer portions of the gate stack.

An exemplary method for forming a gate stack of a multigate device includes forming a gate dielectric over a channel layer and forming a gate electrode over the gate dielectric. Forming the gate electrode includes forming a work function layer over the gate dielectric and forming a cap over the work function layer. Forming the cap includes forming a metal nitride layer over the work function layer and forming a silicon-comprising layer over the metal nitride layer. Forming the gate electrode includes forming a fluorine-free tungsten layer over the silicon-comprising layer of the cap without breaking vacuum. Forming the fluorine-free tungsten layer over the silicon-comprising layer includes co-flowing a tungsten-comprising precursor (e.g., WCl5) and a hydrogen-comprising precursor (e.g., H2).

Multi-gate devices and methods for fabricating such are disclosed herein. An exemplary method includes forming a gate dielectric layer around first channel layers in a p-type gate region and around second channel layers in an n-type gate region. Sacrificial features are formed between the second channel layers in the n-type gate region. A p-type work function layer is formed over the gate dielectric layer in the p-type gate region and the n-type gate region. After removing the p-type work function layer from the n-type gate region, the sacrificial features are removed from between the second channel layers in the n-type gate region. An n-type work function layer is formed over the gate dielectric layer in the n-type gate region. A metal fill layer is formed over the p-type work function layer in the p-type gate region and the n-type work function layer in the n-type gate region.

An exemplary method for forming a gate stack of a multigate device includes forming a gate dielectric over a channel layer and forming a gate electrode over the gate dielectric. Forming the gate electrode includes forming a work function layer over the gate dielectric and forming a cap over the work function layer. Forming the cap includes forming a metal nitride layer over the work function layer and forming a silicon-comprising layer over the metal nitride layer. Forming the gate electrode includes forming a fluorine-free tungsten layer over the silicon-comprising layer of the cap without breaking vacuum. Forming the fluorine-free tungsten layer over the silicon-comprising layer includes co-flowing a tungsten-comprising precursor (e.g., WCl5) and a hydrogen-comprising precursor (e.g., H2).

An exemplary device includes a stack of channel layers over a substrate extension, a gate, and an insulation layer. The stack of channel layers extends between a first epitaxial source / drain and a second epitaxial source / drain. The gate surrounds each channel layer of the stack of the channel layers. The insulation layer is over the substrate extension, the gate is between a bottommost channel layer of the stack of channel layers and the insulation layer, and the insulation layer is between the gate and the substrate extension. The insulation layer extends between the first epitaxial source / drain and the second epitaxial source / drain, each of which may include an undoped epitaxial layer. A top surface of the undoped epitaxial layer is below a bottom surface of the bottommost channel layer and / or above a top surface of the insulation layer. The insulation layer may wrap the substrate extension and / or have an air gap therein.

Multigate devices having bottom insulation and methods of fabrication thereof are disclosed herein. An exemplary bottom channel insulation structure includes a first insulation layer disposed over a substrate (e.g., an extension thereof) and a second insulation layer disposed over the first insulation layer. The first insulation layer has a first composition and a first length. The second insulation layer has a second composition that is different than the first composition and a second length that is greater than the first length. The first insulation layer is a bottom sacrificial layer of a set of sacrificial layers that are formed and subsequently replaced with a gate stack during fabrication of a multigate device. The bottom sacrificial layer is a dummy sacrificial layer because is not replaced with the gate stack, such that additional insulation is provided between the gate stack and the substrate and / or between source / drains.

Methods include providing a first fin structure and a second fin structure each extending from a substrate. A first gate-all-around (GAA) transistor is formed on the first fin structure; the first GAA transistor has a channel region within a first plurality of nanostructures. A second GAA transistor is formed on the second fin structure; the second GAA transistor has a second channel region configuration. The second GAA transistor has a channel region within a second plurality of nanostructures. The second plurality of nanostructures is less than the first plurality of nanostructures.

Multi-gate devices and methods for fabricating such are disclosed herein. An exemplary method includes forming a semiconductor stack on a substrate, wherein the semiconductor stack includes a first semiconductor layers and a second semiconductor layers alternatively disposed, the first semiconductor layers and the second semiconductor layers being different in composition; patterning the semiconductor stack to form a semiconductor fin; forming a dielectric fin next to the semiconductor fin; forming a first gate stack on the semiconductor fin and the dielectric fin; etching to a portion of the semiconductor fin within a source / drain region, resulting in a source / drain recess; and epitaxially growing a source / drain feature in the source / drain recess, defining an airgap spanning between a sidewall of the source / drain feature and a sidewall of the dielectric fin.

Multigate devices and methods for fabricating such are disclosed herein. An exemplary multigate device includes a first FET disposed in a first region; and a second FET disposed in a second region of a substrate. The first FET includes first channel layers disposed over the substrate, and a first gate stack disposed on the first channel layers and extended to warp around each of the first channel layers. The second FET includes second channel layers disposed over the substrate, and a second gate stack disposed on the second channel layers and extended to warp around each of the second channel layers. A number of the first channel layers is greater than a number of the second channel layers. A bottommost one of the first channel layers is below a bottommost one of the second channel layers.

Epitaxial source / drain structures for enhancing performance of multigate devices, such as fin-like field-effect transistors (FETs) or gate-all-around (GAA) FETs, and methods of fabricating the epitaxial source / drain structures, are disclosed herein. An exemplary device includes a dielectric substrate. The device further includes a channel layer, a gate disposed over the channel layer, and an epitaxial source / drain structure disposed adjacent to the channel layer. The channel layer, the gate, and the epitaxial source / drain structure are disposed over the dielectric substrate. The epitaxial source / drain structure includes an inner portion having a first dopant concentration and an outer portion having a second dopant concentration that is less than the first dopant concentration. The inner portion physically contacts the dielectric substrate, and the outer portion is disposed between the inner portion and the channel layer. In some embodiments, the outer portion physically contacts the dielectric substrate.

The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a fin region formed on a substrate, wherein the fin region includes multiple channels vertically stacked on the substrate; a gate stack disposed on the fin region, wherein the gate stack is wrapping around each of the multiple channels and includes gate extensions being extending laterally to be overlapped with inner spacers; and a pair of source / drain (S / D) features formed on the fin region, interposed by the gate stack, and connected with the multiple channels.

Methods and devices of providing tensile / compressive stressor layers for gate-all-around devices. A first GAA device and a second GAA are disposed having a shallow trench isolation feature and one of more stressor layers between gate structures of the first GAA device and the second GAA. The stressor layers can provide tensile stress to a channel layer of the first GAA device and a compressive stress to another channel layer of the second GAA device.

Epitaxial source / drain structures for enhancing performance of multigate devices, such as fin-like field-effect transistors (FETs) or gate-all-around (GAA) FETs, and methods of fabricating the epitaxial source / drain structures, are disclosed herein. An exemplary source / drain structure extends from a topmost channel layer to a depth into a semiconductor substrate. The source / drain structure includes an undoped epitaxial layer with a trough-shaped top surface, a first doped epitaxial layer over the undoped epitaxial layer, a second doped epitaxial layer over the first epitaxial layer, and a third doped epitaxial layer over the second doped epitaxial layer. A thickness of the undoped epitaxial layer is less than the depth of the epitaxial source / drain structure into the semiconductor substrate. The thickness and the depth are tuned based on a size of an active region to which the epitaxial source / drain structure belongs, such that the epitaxial source / drain structure mitigates short channel effects while optimizing performance.

Device comprising: having a multi-gate device (200, 200', 200"): a first channel layer (208) and a second channel layer (208) arranged between a source feature (1702A) and a drain feature (1702B), wherein the second channel layer (208) is the channel layer of the multigate device (200, 200', 200") that is closest to a front face of the multigate device (200, 200', 200"); a metal gate (2202-2208) surrounding the first channel layer (208) and the second channel layer (208), a first air gap spacer (2702, 2702', 2702") located between the metal gate (2202-2208) and the source feature (1702A), and a second air gap spacer (2702, 2702', 2702") located between the metal gate (2202-2208) and the drain feature (1702B); a rear contact (3002) extending to the source feature (1702A); a current-conducting metallization layer (3004) connected to the rear contact (3002); and a residue (1402') of dielectric material next to the first air gap spacer (2702") and adjacent to the second channel layer (208), wherein the first air gap spacer (2702") exposes the first channel layer (208).

Self-aligned gate cutting techniques are disclosed herein that provide dielectric gate isolation fins for isolating gates of multigate devices from one another. An exemplary device includes a first multigate device having first source / drain features and a first metal gate that surrounds a first channel layer and a second multigate device having second source / drain features and a second metal gate that surrounds a second channel layer. A dielectric gate isolation fin separates the first metal gate from the second metal gate. The dielectric gate isolation fin includes a first dielectric layer having a first dielectric constant and a second dielectric layer having a second dielectric constant disposed over the first dielectric layer. The second dielectric constant is greater than the first dielectric constant. The first metal gate and the second metal gate physically contact the first channel layer and the second channel layer, respectively, and the dielectric gate isolation fin.

A semiconductor structure includes a first multigate device, a second multigate device, and an isolation structure. The first multigate device has a first channel layer extending between first epitaxial source / drains along a first direction. The second multigate device has a second channel layer extending between second epitaxial source / drains along the first direction. The first epitaxial source / drains and second epitaxial source / drains have a first width and a second width, respectively, along a second direction that is different than the first direction. The isolation structure includes a dielectric fin over a substrate isolation feature. The dielectric fin is between the first epitaxial source / drains and the second epitaxial source / drains. The dielectric fin has a third width along the second direction. A distance between the first epitaxial source / drains and the second epitaxial source / drains along the second direction is greater than the third width, less than the second width, and less than the first width.

Source / drain silicide that improves performance and methods for fabricating such are disclosed herein. An exemplary device includes a first channel layer disposed over a substrate, a second channel layer disposed over the first channel layer, and a gate stack that surrounds the first channel layer and the second channel layer. A source / drain feature disposed adjacent the first channel layer, second channel layer, and gate stack. The source / drain feature is disposed over first facets of the first channel layer and second facets of the second channel layer. The first facets and the second facets have a (111) crystallographic orientation. An inner spacer disposed between the gate stack and the source / drain feature and between the first channel layer and the second channel layer. A silicide feature is disposed over the source / drain feature where the silicide feature extends into the source / drain feature towards the substrate to a depth of the first channel layer.

The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a fin region formed on a substrate, wherein the fin region includes multiple channels vertically stacked on the substrate; a gate stack disposed on the fin region, wherein the gate stack is wrapping around each of the multiple channels and includes gate extensions being extending laterally to be overlapped with inner spacers; and a pair of source / drain (S / D) features formed on the fin region, interposed by the gate stack, and connected with the multihple channels.

Methods for fabricating multigate transistors using dummy oxide interposers are disclosed herein. An exemplary method comprises fabricating a multilayer stack having first semiconductor layers, sacrificial semiconductor layers, and a substrate extension. A source / drain recess is fabricated by removing the first semiconductor layers, the sacrificial semiconductor layers, and a portion of the substrate extension in a source / drain region, and a source / drain structure is fabricated in the source / drain recess. The source / drain structure has a second semiconductor layer and an insulator layer, and the insulator layer is placed between the second semiconductor layer and the substrate extension. Prior to fabricating the source / drain structure, the sacrificial semiconductor layers are replaced with dielectric sacrificial layers.After fabricating the source / drain structure, the dielectric sacrificial layers are removed from a channel region to form part of a gate opening. A gate stack is then fabricated within this portion of the gate opening.

Gate isolation techniques disclosed herein form gate isolation fins to isolate metal gates of multigate devices from one another before forming the multigate devices, and in particular, before forming the metal gates of the multigate devices. An exemplary device includes a first multigate device having first source / drain features and a first metal gate that surrounds a first channel layer and a second multigate device having second source / drain features and a second metal gate that surrounds a second channel layer. A gate isolation fin, which separates the first metal gate and the second metal gate, includes a dielectric feature having a first dielectric layer having a first dielectric constant (e.g., a low-k dielectric core) and a second dielectric layer (e.g., a high-k dielectric shell) surrounding the first dielectric layer. The second dielectric layer has a second dielectric constant that is greater than the first dielectric constant.

Semiconductor devices having improved source / drain features and methods for fabricating such are disclosed herein. An exemplary device includes a semiconductor layer stack disposed over a mesa structure of a substrate. The device further includes a metal gate disposed over the semiconductor layer stack and an inner spacer disposed on the mesa structure of the substrate. The device further includes a first epitaxial source / drain feature and a second epitaxial source / drain feature where the semiconductor layer stack is disposed between the first epitaxial source / drain feature and the second epitaxial source / drain feature. The device further includes a void disposed between the inner spacer and the first epitaxial source / drain feature.

Self-aligned gate cutting techniques for multigate devices are disclosed herein that provide multigate devices having asymmetric metal gate profiles and asymmetric source / drain feature profiles. An exemplary multigate device has a channel layer, a metal gate that wraps a portion of the channel layer, and source / drain features disposed over a substrate. The channel layer extends along a first direction between the source / drain features. A first dielectric fin and a second dielectric fin are disposed over the substrate and configured differently. The channel layer extends along a second direction between the first dielectric fin and the second dielectric fin. The metal gate is disposed between the channel layer and the second dielectric fin. In some embodiments, the first dielectric fin is disposed on a first isolation feature, and the second dielectric fin is disposed on a second isolation feature. The first isolation feature and the second isolation feature are configured differently.

A semiconductor structure includes a first multigate device, a second multigate device, and an isolation structure. The first multigate device has a first channel layer extending between first epitaxial source / drains along a first direction. The second multigate device has a second channel layer extending between second epitaxial source / drains along the first direction. The first epitaxial source / drains and second epitaxial source / drains have a first width and a second width, respectively, along a second direction that is different than the first direction. The isolation structure includes a dielectric fin over a substrate isolation feature. The dielectric fin is between the first epitaxial source / drains and the second epitaxial source / drains. The dielectric fin has a third width along the second direction. A distance between the first epitaxial source / drains and the second epitaxial source / drains along the second direction is greater than the third width, less than the second width, and less than the first width.

Self-aligned gate cutting techniques for multigate devices are disclosed herein that provide multigate devices having asymmetric metal gate profiles and asymmetric source / drain feature profiles. An exemplary multigate device has a channel layer, a metal gate that wraps a portion of the channel layer, and source / drain features disposed over a substrate. The channel layer extends along a first direction between the source / drain features. A first dielectric fin and a second dielectric fin are disposed over the substrate and configured differently. The channel layer extends along a second direction between the first dielectric fin and the second dielectric fin. The metal gate is disposed between the channel layer and the second dielectric fin. In some embodiments, the first dielectric fin is disposed on a first isolation feature, and the second dielectric fin is disposed on a second isolation feature. The first isolation feature and the second isolation feature are configured differently.

An exemplary method includes forming an opening in an interlevel dielectric (ILD) layer. The opening in the ILD layer exposes a doped epitaxial layer. The method further includes performing an in-situ doping deposition process, an annealing process, and an etching process to form a doped semiconductor layer over the doped epitaxial layer. The doped semiconductor layer partially fills the opening. The method further includes forming a metal-comprising structure that fills a remainder of the opening. The metal-comprising structure is disposed over a top and sidewalls of the doped epitaxial layer. The doped semiconductor layer is disposed between the metal-comprising structure and the top of the doped epitaxial layer and between the metal-comprising structure and the sidewalls of the doped epitaxial layer. The in-situ deposition process may implement a temperature less than about 350° C. The doped epitaxial layer includes p-type dopant (e.g., boron), and the doped semiconductor layer includes gallium.

Self-aligned gate isolation / cutting techniques for multigate devices are disclosed herein. An exemplary multigate device includes a first gate having a gate stack that surrounds a semiconductor layer. The first gate is disposed between a first gate isolation wall and a second gate isolation wall. The gate stack has a gate dielectric and a gate electrode, the gate stack has a first sidewall and a second sidewall, and the first sidewall is formed by the gate dielectric and the gate electrode. A gate endcap is disposed on the first sidewall. A gate helmet is disposed over the gate stack, and a portion of the gate dielectric is disposed between the gate electrode and the gate helmet. A gate contact is disposed on the first gate. The gate contact extends over the first gate isolation wall and connects the first gate to a second gate.