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Inter-chip processor control plane communication

A control plane and processor technology, applied in the field of communication between multiple processors, which can solve problems such as long delay and waste of processing resources

Inactive Publication Date: 2007-12-12
CISCO TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Besides inducing long delays, this approach can waste considerable processing resources

Method used

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  • Inter-chip processor control plane communication
  • Inter-chip processor control plane communication
  • Inter-chip processor control plane communication

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Embodiment Construction

[0020] 1 is a block diagram of a computer network 100 that includes a collection of interconnected communication media and subnetworks to which multiple stations are attached. The stations are typically a plurality of computers including end stations 102 , 112 and intermediate station 200 . Intermediate stations 200 may be routers or network switches, while end stations 102, 112 may include personal computers or workstations. The subnetworks typically include local area networks (LANs) 110 and 120, although other communication media configurations (eg, point-to-point network links) may be more advantageously used by the present invention. Generally, discrete data frames or packets are exchanged between communicating stations according to a predefined protocol, so that communication can be realized between various stations in the network. For the exemplary embodiments described here, the predefined protocol is the Internet Protocol (IP), although other protocols may be used to...

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Abstract

An inter-chip communication (ICC) mechanism enables any processor in a pipelined arrayed processing engine to communicate directly with any other processor of the engine over a low-latency communication path. The ICC mechanism includes a unidirectional control plane path that is separate from a data plane path of the engine and that accommodates control information flow among the processors. The mechanism thus enables inter-processor communication without sending messages over the data plane communication path extending through processors of each pipeline.

Description

[0001] Cross References to Related Applications [0002] This invention is related to copending application commonly assigned to the assignee of the present invention, US Patent Application Serial No. 09 / 663,777, filed September 18, 2000, entitled "PacketStriping Across a Parallel Header Processor." technical field [0003] The present invention relates to communication between processors, and more particularly to communication between multiple processors of an arrayed processing engine of an intermediate network station. Background technique [0004] Systolic arrays provide a general method for increasing the processing power of computer systems when the problem can be divided into discrete units of work. A one-dimensional systolic array includes a single "row" of processing elements, or processors, with each processor in the array responsible for executing a different set of instructions on input data before passing it on to the next element in the array. To maximize thr...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F15/173G06F9/46G06F15/00G06F15/76H04L12/28H04L12/56H04L29/06
CPCH04L69/12H04L29/06081
Inventor 拉塞尔·施罗特约翰·威廉·马歇尔肯尼思·H·波特
Owner CISCO TECH INC