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Apparatus and method for testing conductive bumps

A technology of conductive bumps and testing devices, which is applied in the direction of measuring devices, semiconductor/solid-state device testing/measurement, single semiconductor device testing, etc., and can solve problems such as labor time-consuming, inapplicable product wafer testing and evaluation, etc.

Inactive Publication Date: 2007-12-26
TAIWAN SEMICON MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, such existing daisy-ring detection methods require a lot of labor and are time-consuming
Furthermore, the above-mentioned daisy-ring detection method is only used for evaluating a bump process and its process parameters, and is not suitable for testing and evaluating product dies in today's integrated circuit industry.

Method used

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  • Apparatus and method for testing conductive bumps
  • Apparatus and method for testing conductive bumps
  • Apparatus and method for testing conductive bumps

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Embodiment Construction

[0031] In order to make the above and other objects, features and advantages of the present invention more comprehensible, a preferred embodiment is specifically cited below, together with the accompanying drawings, and is described in detail as follows:

[0032] An embodiment of the present invention will be described in detail with reference to FIGS. 3 to 7 as follows. 3 to 6 are a series of schematic diagrams for illustrating a conductive bump testing device according to an embodiment of the present invention, and FIG. 7 is a flow chart for illustrating a conductive bump testing method according to an embodiment of the present invention .

[0033] Please refer to FIG. 3 , which illustrates an apparatus 100 for testing conductive bumps. Here, the device 100 includes a support substrate 102 in which a plurality of test probes are formed. The support substrate 102 includes an insulating material such as ceramic material, epoxy, resin, polyimide, FR4 glass fiber, or polymer. ...

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Abstract

The invention relates to a conductive bump test device and method for testing, wherein the conductive bump test device is suitable for testing a plurality of conductive bumps and comprises a support base and a first probe, a second probe and a plurality of double-probe group that are arranged in the support base, wherein each double-probe group comprises two electrically connected third probes. The conductive bump test device and the method for testing of the invention can be immediately applied after forming the bump, which is convenient to timely test the formed bump quality and the applied bump procedure.

Description

technical field [0001] The present invention relates to wafer-level bumps testing related technologies, and in particular to a testing device and testing method for testing conductive bumps on semiconductor components. Background technique [0002] Flip-chip packaging of electronic products is to directly electrically connect electronic components to a substrate, such as a ceramic substrate, a circuit board, or a substrate using a conductive bump pad carrier, with the active surface facing down. Flip-chip technology has rapidly replaced the traditional wire-bonding technology that uses wires to connect the active in-plane pads with the die facing up. [0003] Flip-chip packaging technology is usually achieved by placing solder bumps on a silicon wafer. The solder bump flip-chip process usually includes four consecutive process steps, including: (1) preparing a wafer for solder bumping; (2) forming and placing solder bumps on the wafer; (3) placing the wafer The chip with s...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/66G01R31/26
CPCG01R1/07307G01R1/06794
Inventor 郭彦良
Owner TAIWAN SEMICON MFG CO LTD
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