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Shallow trench isolation process

A technology of semiconductors and transistors, applied in the field of semiconductor structures, can solve problems such as device work problems

Inactive Publication Date: 2008-11-26
TAIWAN SEMICON MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Too much strain introduced into the trench can create defects that cause problems with device operation

Method used

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Embodiment Construction

[0031] Figure 1a shows a structure that can be modified for use in conjunction with the invention. In Figure 1a, the substrate 12 is made of a semiconductor, such as Si, Ge or SiGe. Multiple layers, collectively indicated at 13 , are formed on substrate 12 . Multilayer 13 may include a relaxation graded buffer layer 14 disposed over substrate 12 . The graded layer 14 includes, for example, SiGe with a grade rate of, for example, 10% Ge per μm thickness, and a thickness T 1 It is, for example, 1-9 μm.

[0032] Relaxed layer 16 is disposed over graded SiGe layer 14 . The relaxed layer 16 contains, for example, Si 1-x Ge x , where 0.1≤x≤0.9, and the thickness T 2 It is, for example, 0.2-2 μm. In some embodiments, Si 1-x Ge x Can include Si 0.70 Ge 0.30 ,T 2 It may be about 1.5 μm. Relaxed layer 16 may be substantially or fully relaxed, as determined by triaxial X-ray diffraction, and may have 6 dislocation / cm 2 The threading dislocation density of , as determined by ...

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Abstract

A structure including a transistor and a trench structure, with the trench structure inducing only a portion of the strain in a channel region of the transistor.

Description

[0001] related application [0002] This application claims priority to US Provisional Application 60 / 452794, filed March 7, 2003, which is incorporated herein by reference in its entirety. technical field [0003] The present invention relates generally to semiconductor structures, and more particularly to shallow trench isolation. Background technique [0004] Forming an integrated circuit includes defining isolation regions to prevent parasitic current leakage between devices. Isolation technologies include shallow trench isolation (STI) schemes that increase the planarity and packing density of Si very large scale integration (Si VLSI) devices and thus have become the technology node of choice since around 0.25 micrometers (μm) Quarantine scheme. [0005] In a typical STI approach, the active device area is protected by a pad oxide and nitride cap, and isolation trenches are etched around the active device area. After trench etching, a liner oxide is formed in each tr...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/762H01L21/8234H01L29/10H01LH01L21/00H01L21/26H01L21/336H01L21/42H01L21/76H01L21/8238H01L27/00H01L29/00H01L29/06H01L29/772H01L31/0328H01L31/0336H01L31/072H01L31/109
CPCH01L29/1054H01L29/785H01L21/823807H01L29/7842H01L29/66628H01L29/66636H01L21/823878H01L29/6659H01L21/823412H01L21/76224H01L21/76H01L21/762
Inventor M·T·柯里A·J·洛赫特费尔德
Owner TAIWAN SEMICON MFG CO LTD
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