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Method and apparatus for monitoring number of lanes between controller and PCI express device

A technology of controllers and information processing devices, which is applied to instruments, electrical digital data processing, calculations, etc., and can solve problems such as errors and storage devices that cannot reach high speeds

Inactive Publication Date: 2009-01-28
FUJITSU LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

For example, the storage device cannot achieve the high speed required by the device
Also, if the system continues to function without detecting a failure in one part of the system, a series of failures can lead to serious errors

Method used

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  • Method and apparatus for monitoring number of lanes between controller and PCI express device
  • Method and apparatus for monitoring number of lanes between controller and PCI express device
  • Method and apparatus for monitoring number of lanes between controller and PCI express device

Examples

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Embodiment Construction

[0019] Exemplary embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0020] figure 2 The block diagram of shows an information processing device according to an embodiment of the present invention. The information processing apparatus 10 includes system boards 100 to 103 having processors and memories, I / O units 200 to 203 for connecting various PCI Express devices to the information processing apparatus 10, and system boards 100 to 103 and I / O units for connecting the system boards 100 to 103 to the information processing apparatus 10. A crossbar (XB) 300 to which / O cells 200 to 203 are connected. The number of system boards and I / O units connected to the crossbar switch 300 is not limited to figure 2 4 shown.

[0021] A management board (MMB) 400 is connected to the system boards 100 to 103, the I / O units 200 to 203, and the crossbar switch 300, respectively. The MMB 400 executes various management proc...

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PUM

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Abstract

After the initialization of the information processing apparatus, the MMB reads out a value in the Negotiated Link Width register and stores the value in a RAM. When receiving an interrupt from the I / O bridge, the MMB reads out a value in the Negotiated Link Width register again and compares the value with the value stored in the RAM. When both the values are different, the MMB transmits a message to a console and takes predetermined measures, such as separation of the device.

Description

technical field [0001] The present invention relates to methods and apparatus for monitoring the number of channels between a controller and a PCI Express device. Background technique [0002] With the rapid increase in processing speed of processors, various interfaces for processors are required to work at higher speeds. For example, a Peripheral Component Interconnect (PCI) that has been used to connect a processor in a personal computer and various devices has a transfer rate of about 133 MB / sec. However, the performance of the processor is not fully utilized at this transfer rate. Therefore, PCI is gradually being replaced by a new interface called PCI Express that can achieve higher transfer rates. [0003] PCI Express uses a serial interface instead of the traditional parallel interface. Serial interfaces increase processing speed because, unlike parallel interfaces, they do not require synchronization of signals and are less susceptible to noise. PCI Express has ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F13/00
CPCG06F2213/0026G06F13/385G06F13/20G06F11/00G06F13/14
Inventor 须江智志
Owner FUJITSU LTD
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