Trench isolation technology and method

Abstract

A method of manufacturing an integrated circuit (IC) utilizes a shallow trench isolation (STI) technique. The shallow trench isolation technique is used in strained silicon (SMOS) process. The liner for the trench is formed from a layer deposited in a low temperature process which reduces germanium outgassing. The low temperature process can be an LPCVD. An annealing step can form the liner.

Description

field of invention [0001] The invention relates to an integrated circuit (integrated circuit, IC) device and a process for manufacturing the IC device. More specifically, the present invention relates to a method of forming a trench isolation structure on a germanium-containing substrate or a germanium-containing layer. Background technique [0002] An integrated circuit (IC) contains many transistors formed on a semiconductor substrate. Many methods are known for forming transistors on semiconductor substrates. Typically transistors are isolated from each other by insulating or isolating structures. [0003] One method of forming transistors on a silicon substrate is the well-known Local Oxidation of Silicon (LOCOS) process. The traditional LOCOS process usually includes the following simplified steps. First, a silicon nitride layer is thermally grown on a silicon substrate. Traditional LOCOS processes typically require a high-quality, thermally grown silicon nitride l...

AI Technical Summary

Problems solved by technology

For example, the traditional STI pad oxide process uses temperatures around 1000°C, which increases germanium outgassing

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