Programmable non-volatile semiconductor memory device

Abstract

The present invention relates to a programmable non-volatile semiconductor memory device comprising a matrix of rows and columns of memory cells (1). To reduce the required memory area a 3T memory cell is proposed comprising a bridge of two bridge transistors (MN0, MN1), preferably NMOS transistors, a read transistor, preferably an PMOS transistor, and a silicided polysilicium fuse resistor (R). The read transistors enable the use of a single sense line (SL) for all memory cells (1) of the same row or column in the matrix thus enabling the use of a common sense amplifier for sensing memory cells (1).

Description

technical field [0001] The invention relates to a programmable non-volatile semiconductor storage device, which includes a matrix composed of multiple rows and multiple columns of memory cells. Background technique [0002] Such a semiconductor memory device is known from WO 02 / 43152, which has a one-time programmable (OTP) structure using self-aligned silicided (SALICIDE) polysilicon fuses. In one embodiment, the OTP structure is arranged as a fuse element surrounded by a switching transistor. In order to construct a transistor with sufficient drive capability to program a fuse element, the gate geometry of the transistor is arranged in a serpentine or equivalent pattern. The disclosed configuration has the read and write circuits on opposite sides of the array. Each time a fuse is programmed with a write current, all gates within a column can be read simultaneously. [0003] The OTP ROM is an array of memory cells with fuse links. The fuse link is broken by applying a ...

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Problems solved by technology

However, in order to read memory cells, that is, to detect whether the memory cells are programmed, each memory cel

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