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A multiple-chip structure and multiple-chip electronic device with multiple-chip structure

An electronic device and multi-chip technology, applied in the direction of circuits, electrical components, electrical solid-state devices, etc., can solve the problems of systemic chip development obstacles, low yield, high cost, etc.

Active Publication Date: 2009-09-09
VIA TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the system chip has too many mask processes, the cost is too high, and the yield is too low. Therefore, in actual development, the development of the system chip still has a lot of obstacles

Method used

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  • A multiple-chip structure and multiple-chip electronic device with multiple-chip structure
  • A multiple-chip structure and multiple-chip electronic device with multiple-chip structure
  • A multiple-chip structure and multiple-chip electronic device with multiple-chip structure

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Embodiment Construction

[0033] Figure 1A A schematic side view cross-sectional view showing a multi-chip structure according to the first embodiment of the present invention, Figure 1B draw Figure 1A A schematic top view of the multi-chip structure. Please refer to Figure 1A and Figure 1B The multi-chip structure 100 of the first embodiment includes a chip 110 (such as a north bridge chip or a south bridge chip) and a chip 120 (such as a central processing unit). It must be emphasized that the first embodiment and the following embodiments are described by taking the multi-chip structure of two chips as an example. The multi-chip structure 100 can be configured on a next-level electronic device 10 (such as a packaging substrate, a printed circuit board, or another chip).

[0034] The chip 110 has a buffer area 112 , an interconnection area 114 and a surface 116 , wherein the buffer area 112 and the interconnection area 114 are electrically insulated. In other words, in the chip 110 , there is...

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Abstract

The multi-chip structure comprises: a first chip, which includes a buffer, an inner connection area, and a first surface; wherein, the buffer and connection area are insulated; and a second chip on surface of the first chip connected to the connection area and buffer with a first and second type signal respectively. This invention is low cost and high yield.

Description

technical field [0001] The invention relates to a multi-chip structure and a multi-chip electronic device with the multi-chip structure, in particular to a multi-chip structure and a multi-chip electronic device which improve the process yield and reduce manufacturing costs. Background technique [0002] In the semiconductor industry, the production of integrated circuits (IC) can be mainly divided into three stages: IC design, IC process, and IC package. [0003] In the fabrication of integrated circuits, chips are completed through wafer fabrication, integrated circuit formation, and wafer sawing. The chip has an active surface, which generally refers to the surface of the chip with active elements. After the integrated circuit inside the wafer is completed, the active surface of the wafer is further equipped with a plurality of bonding pads, so that the chips formed by dicing the wafer can be electrically connected to a carrier outside through these pads ( carrier). Th...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L25/00H01L25/065H01L23/488
CPCH01L2224/73253H01L2224/32145H01L2224/16145H01L2224/48145H01L2224/16225H01L2224/73265H01L24/73H01L2924/14
Inventor 许志行
Owner VIA TECH INC