Method for measuring capacitance mismatch and circuit structure thereof
A capacitance mismatch and capacitance technology, which is applied in the direction of measuring electricity, measuring resistance/reactance/impedance, measuring electrical variables, etc., to achieve the effect of shortening the design cycle
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[0012] Such as figure 1 As shown, it is a structural diagram of a capacitance Mismatch test circuit in a specific embodiment of the present invention, specifically including: a proposed test capacitor C1, a proposed test capacitor C2, a reference capacitor Cref, a PMOS transistor M0, a PMOS transistor M1, and a PMOS transistor three M2, NMOS transistor 1 M3, NMOS transistor 2 M4, NMOS transistor 3 M5, signal generator, wherein the gates of PMOS transistor 1 M0, PNMOS transistor 2 M1 and PMOS transistor 3 M2 are coupled and connected to the signal generator, PMOS The source and substrate of tube 1 M0, PMOS tube 2 M1 and PMOS tube 3 M2 are connected to the working power supply, the drain of PMOS tube 1 M0 is connected to the proposed test capacitor C1, the drain of PMOS tube 2 M1 is connected to the reference capacitor Cref, PMOS The drain of tube three M2 is connected to the test capacitor two C2; the gates of NMOS tube one M3, NMOS tube two M4, and NMOS tube three M5 are coupl...
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