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Method for measuring capacitance mismatch and circuit structure thereof

A capacitance mismatch and capacitance technology, which is applied in the direction of measuring electricity, measuring resistance/reactance/impedance, measuring electrical variables, etc., to achieve the effect of shortening the design cycle

Active Publication Date: 2009-10-21
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The charging capacitance test method (Charge-Based Capacitance Measurement, CBCM) is already a relatively mature and commonly used technology for testing tiny capacitors. For CBCM, please refer to the following paper (Investigation of Interconnect Capacitance Characterization Using Charge-Based Capacitance Measurement (CBCM) Technique and Three -Dimensional Simulation, IEEE JOURNAL OF SOLID-STATECIRCUITS, VOL.33, NO.3, MARCH 1998), the CBCM method can control the accuracy of the test capacitance within the range of 0.01fF, but the industry has not used this method for capacitance Mismatch Measurement

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  • Method for measuring capacitance mismatch and circuit structure thereof
  • Method for measuring capacitance mismatch and circuit structure thereof

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Embodiment

[0012] Such as figure 1 As shown, it is a structural diagram of a capacitance Mismatch test circuit in a specific embodiment of the present invention, specifically including: a proposed test capacitor C1, a proposed test capacitor C2, a reference capacitor Cref, a PMOS transistor M0, a PMOS transistor M1, and a PMOS transistor three M2, NMOS transistor 1 M3, NMOS transistor 2 M4, NMOS transistor 3 M5, signal generator, wherein the gates of PMOS transistor 1 M0, PNMOS transistor 2 M1 and PMOS transistor 3 M2 are coupled and connected to the signal generator, PMOS The source and substrate of tube 1 M0, PMOS tube 2 M1 and PMOS tube 3 M2 are connected to the working power supply, the drain of PMOS tube 1 M0 is connected to the proposed test capacitor C1, the drain of PMOS tube 2 M1 is connected to the reference capacitor Cref, PMOS The drain of tube three M2 is connected to the test capacitor two C2; the gates of NMOS tube one M3, NMOS tube two M4, and NMOS tube three M5 are coupl...

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PUM

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Abstract

The invention discloses a method for measuring the mismatch of capacitance and the circuit organization. The circuit comprises capacitance I for test, capacitance II for test, reference capacitance, NMOS tube I, NMOS tube II, NMOS tube III, PMOS tube I, PMOS tube II, PMOS tube III and a signal generator. The method for measuring the mismatch of capacitance comprises: firstly, turn off NMOS and PMOS when the circuit is working; secondly, cut off NMOS and conduct PMOS to make the capacitances charged; thirdly, cut off PMOS and conduct NMOS to make the capacitances discharged; measure the average current Iref, I1 and I2 flowing through the reference capacitance, capacitance I for test and capacitance II for test separately; calculate the Mismatch value of the capacitance C< mismatch >, that is C< mismatch > equals to (I1-I2) / Vf, wherein, f is the circuit working frequency and V is the working voltage. The invention adopts charging capacitance testing method with high precision to measure the capacitance Mismatch, which can offer exact testing data for the extraction of capacitance Mismatch model, and the design cycle of mimic channel can be shortened greatly.

Description

technical field [0001] The invention relates to a technology for measuring capacitance mismatch in semiconductor integrated circuits, in particular to a method for measuring capacitance mismatch and its circuit structure. Background technique [0002] In analog circuit design, device Mismatch (mismatch) characteristics play a crucial role in the design of analog circuits. In the research process of capacitor Mismatch, how to accurately measure the mismatch value between capacitors is even more important. At present, a common method for measuring capacitance mismatch is to directly measure the absolute value of two capacitances by using a capacitance tester (such as: Agilent4284), and obtain capacitance mismatch by calculating their capacitance difference. The disadvantage of this method is that the accuracy of the conventional capacitance tester is not high, and the accuracy of the conventional capacitance tester is only on the order of pF, and the error when directly using...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G01R27/26G01R31/00
Inventor 徐向明武洁
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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