Architecture for assisted-charge memory array
A charge memory, memory array technology, applied in static memory, read-only memory, information storage, etc., can solve problems such as long programming time
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[0044] FIG. 1 is a diagram of an auxiliary charge memory device 100 configured in accordance with an embodiment of the described systems and methods. The auxiliary charge memory device 100 includes a transistor including a silicon substrate 102 . The silicon substrate 102 may become the substrate material upon which other memory devices 100 are fabricated. Two n+ regions 104 and 106 can be produced by doping the silicon substrate 102 . These regions 104 and 106 can act as the source and drain of the transistor, respectively. ONO layer 108 can be disposed over silicon substrate 102 and between n+ regions 104 and 106 . A polysilicon layer (not shown here) can be placed over the ONO layer 108 to form the gate electrode of the transistor.
[0045] The ONO layer 108 includes a nitride layer 110 between two oxide layers that can trap charges. For example, electrons moving up through the bottom oxide layer are trapped in the nitride layer. These electrons can form auxiliary char...
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