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Architecture for assisted-charge memory array

A charge memory, memory array technology, applied in static memory, read-only memory, information storage, etc., can solve problems such as long programming time

Active Publication Date: 2007-07-25
MACRONIX INT CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0007] Programming using band-to-band hot hole injection may still be too slow and may require too long programming times for some applications

Method used

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  • Architecture for assisted-charge memory array
  • Architecture for assisted-charge memory array
  • Architecture for assisted-charge memory array

Examples

Experimental program
Comparison scheme
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Embodiment Construction

[0044] FIG. 1 is a diagram of an auxiliary charge memory device 100 configured in accordance with an embodiment of the described systems and methods. The auxiliary charge memory device 100 includes a transistor including a silicon substrate 102 . The silicon substrate 102 may become the substrate material upon which other memory devices 100 are fabricated. Two n+ regions 104 and 106 can be produced by doping the silicon substrate 102 . These regions 104 and 106 can act as the source and drain of the transistor, respectively. ONO layer 108 can be disposed over silicon substrate 102 and between n+ regions 104 and 106 . A polysilicon layer (not shown here) can be placed over the ONO layer 108 to form the gate electrode of the transistor.

[0045] The ONO layer 108 includes a nitride layer 110 between two oxide layers that can trap charges. For example, electrons moving up through the bottom oxide layer are trapped in the nitride layer. These electrons can form auxiliary char...

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Abstract

An Assisted Charge (AC) Memory cell includes a transistor that includes, for example, a p-type substrate with an n+ source region and an n+ drain region implanted on the p-type substrate. A gate electrode can be formed over the substrate and portions of the source and drain regions. The gate electrode can include a trapping layer. The trapping layer can be treated as electrically split into two sides. One side can be referred to as the AC-side and can be fixed at a high voltage by trapping electrons within the layer. The electrons are referred to as assisted charges. The other side of can be used to store data and is referred to as the data-side. The abrupt electric field between AC-side and the data-side can enhance programming efficiency.

Description

technical field [0001] The present invention relates to semiconductor memory devices, and more particularly, to semiconductor memory devices including an auxiliary charge (AC). Background technique [0002] Conventional electrically programmable read only memory (EPROM) trench oxide (ETOX) flash memory cells and conventional nitride ROM cells are limited by inefficient programming because of the large currents required to perform programming operations. ETOX flash memory and Nitride ROM cells are programmed using channel hot electron (CHE) injection in such a way that the cell is programmed to a high voltage. Hot electrons are electrons that are accelerated to very high kinetic energies in the region of a strong electric field in a semiconductor device, such as ETOX or Nitride ROM semiconductor devices. Channel hot electron injection occurs when the gate and drain voltages are much higher than the source voltage. [0003] Channel carriers moving from source to drain are so...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/115H01L29/792G11C16/02G11C16/10
CPCG11C16/0466G11C16/0491G11C16/0475
Inventor 吴昭谊李明修郭明昌
Owner MACRONIX INT CO LTD