Fabrication and structures of crystalline material

a technology of crystalline materials and fabrication, applied in the direction of basic electric elements, electrical equipment, semiconductor devices, etc., to achieve the effect of reducing surface roughness, reducing surface roughness, and reducing surface roughness
US20100072515A1Inactive Publication Date: 2010-03-25TAIWAN SEMICON MFG CO LTD

Patent Information

Authority / Receiving Office
US · United States
Current Assignee / Owner
TAIWAN SEMICON MFG CO LTD
Publication Date
2010-03-25
Estimated Expiration
Not applicable · inactive patent

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Abstract

A surface of the first semiconductor crystalline material has a reduced roughness. A semiconductor device includes a low defect, strained second semiconductor crystalline material over the surface of the first crystalline material. A surface of the strained second semiconductor crystalline material has a reduced roughness. One example includes obtaining a surface with reduced roughness by creating process parameters that reduce impurities at an interfacial boundary between the first and second semiconductor crystalline materials. In one embodiment, the first semiconductor crystalline material can be confined by an opening in an insulator having an aspect ratio sufficient to trap defects using Aspect Ratio Trapping techniques.
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Description

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] The present application claims priority from U.S. provisional patent application Ser. No. 61 / 098,734, filed Sep. 19, 2008, by Ji-Soo Park and James G. Fiorenza entitled “IMPROVED FABRICATION AND STRUCTURES OF CRYSTALLINE MATERIAL” and incorporated by reference herein and for which benefit of the priority date is hereby claimed.BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] The present invention relates to fabrication or structures including a semiconductor crystalline material. For example, improved epitaxial growth or structures may occur over a planarized surface including a semiconductor crystalline material.

[0004] 2. Description of the Related Art

[0005] This section provides background information and introduces information related to various aspects of the disclosure that are described and / or claimed below. These background statements are not admissions of prior art.

[0006] Integration of lattice-mismatched semiconductor...

Claims

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