Fabrication and structures of crystalline material

a technology of crystalline materials and fabrication, applied in the direction of basic electric elements, electrical equipment, semiconductor devices, etc., to achieve the effect of reducing surface roughness, reducing surface roughness, and reducing surface roughness

Inactive Publication Date: 2010-03-25
TAIWAN SEMICON MFG CO LTD
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  • Abstract
  • Description
  • Claims
  • Application Information

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Benefits of technology

[0015]Therefore, it is an aspect of one embodiment of the invention to provide an epitaxially grown semiconductor crystalline material with a reduced surface roughness.
[0016]An alternative aspect of one embodiment of the invention is to provide a semiconductor crystalline material with a reduced surface roug

Problems solved by technology

However, planarization is typically required for device fabrication because deviations from a flat surface can lead to device faul

Method used

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  • Fabrication and structures of crystalline material
  • Fabrication and structures of crystalline material
  • Fabrication and structures of crystalline material

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Embodiment Construction

[0033]Reference will now be made in detail to the embodiments of the present general inventive concept, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to like elements throughout. The embodiments are described below in order to explain the present general inventive concept by referring to the figures.

[0034]The formation of lattice-mismatched materials has many practical applications. For example, heteroepitaxial growth of group IV materials or compounds, and III-V, III-N and II-VI compounds on a crystalline substrate, such as silicon, has many applications such as photovoltaics, resonant tunneling diodes (RTD's), transistors (e.g., FET (which can be planar or 3D (e.g., finFET), HEMT, etc.), light-emitting diodes and laser diodes. As one example, heteroepitaxy of germanium on silicon is considered a promising path for high performance p-channel metal-oxide-semiconductor (MOS) field-effect transistors (FET) and for integrating opt...

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Abstract

A surface of the first semiconductor crystalline material has a reduced roughness. A semiconductor device includes a low defect, strained second semiconductor crystalline material over the surface of the first crystalline material. A surface of the strained second semiconductor crystalline material has a reduced roughness. One example includes obtaining a surface with reduced roughness by creating process parameters that reduce impurities at an interfacial boundary between the first and second semiconductor crystalline materials. In one embodiment, the first semiconductor crystalline material can be confined by an opening in an insulator having an aspect ratio sufficient to trap defects using Aspect Ratio Trapping techniques.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS[0001]The present application claims priority from U.S. provisional patent application Ser. No. 61 / 098,734, filed Sep. 19, 2008, by Ji-Soo Park and James G. Fiorenza entitled “IMPROVED FABRICATION AND STRUCTURES OF CRYSTALLINE MATERIAL” and incorporated by reference herein and for which benefit of the priority date is hereby claimed.BACKGROUND OF THE INVENTION[0002]1. Field of the Invention[0003]The present invention relates to fabrication or structures including a semiconductor crystalline material. For example, improved epitaxial growth or structures may occur over a planarized surface including a semiconductor crystalline material.[0004]2. Description of the Related Art[0005]This section provides background information and introduces information related to various aspects of the disclosure that are described and / or claimed below. These background statements are not admissions of prior art.[0006]Integration of lattice-mismatched semiconductor...

Claims

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Application Information

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IPC IPC(8): H01L29/02H01L21/20
CPCH01L21/02494H01L21/02532H01L21/02538H01L29/165H01L21/02636H01L21/02658H01L21/02694H01L21/02551H01L21/02057H01L21/02381H01L21/0262H01L29/161H01L29/32
Inventor PARK, JI-SOOFIORENZA, JAMES G.
Owner TAIWAN SEMICON MFG CO LTD
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