Fabrication and structures of crystalline material

Abstract

A surface of the first semiconductor crystalline material has a reduced roughness. A semiconductor device includes a low defect, strained second semiconductor crystalline material over the surface of the first crystalline material. A surface of the strained second semiconductor crystalline material has a reduced roughness. One example includes obtaining a surface with reduced roughness by creating process parameters that reduce impurities at an interfacial boundary between the first and second semiconductor crystalline materials. In one embodiment, the first semiconductor crystalline material can be confined by an opening in an insulator having an aspect ratio sufficient to trap defects using Aspect Ratio Trapping techniques.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS[0001]The present application claims priority from U.S. provisional patent application Ser. No. 61 / 098,734, filed Sep. 19, 2008, by Ji-Soo Park and James G. Fiorenza entitled “IMPROVED FABRICATION AND STRUCTURES OF CRYSTALLINE MATERIAL” and incorporated by reference herein and for which benefit of the priority date is hereby claimed.BACKGROUND OF THE INVENTION[0002]1. Field of the Invention[0003]The present invention relates to fabrication or structures including a semiconductor crystalline material. For example, improved epitaxial growth or structures may occur over a planarized surface including a semiconductor crystalline material.[0004]2. Description of the Related Art[0005]This section provides background information and introduces information related to various aspects of the disclosure that are described and / or claimed below. These background statements are not admissions of prior art.[0006]Integration of lattice-mismatched semiconductor...

AI Technical Summary

Benefits of technology

[0011]In another aspect, one embodiment of the invention can provide clean planarized heteroepitaxial regions suitable for device fabrication and / or devices including the same.

[0012]In another aspect, one embodiment of the invention can provide reduced or low impurity planarized heteroepitaxial regions suitable for device fabrication and / or devices including the same.

[0015]Therefore, it is an aspect of one embodiment of the invention to provide an epitaxially grown semiconductor crystalline material with a reduced surface roughness.

[0016]An alternative aspect of one embodiment of the invention is to provide a semiconductor crystalline material with a reduced surface roughness at a planarized (e.g., different) semiconductor crystalline material.

[0017]An alternative aspect of one embodiment of the invention is to provide an epitaxially grown crystalline material with a reduced surface roughness over an interface having reduced impurities to another grown crystalline material.

Problems solved by technology

However, planarization is typically required for device fabrication because deviations from a flat surface can lead to device fault and / or different device characteristics within an IC or different device characteristics among concurrently manufactured devices.

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