Solid-state image pickup device
一种固体摄像器件、晶体管的技术，应用在晶体管的构造领域，能够解决图像不良、图像信号困难、漏泄电流增加等问题，达到提高像质的效果
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Embodiment approach 1
[0133] FIG. 1 shows a cross-sectional view of a first transistor constituting the solid-state imaging device of Embodiment 1. As shown in FIG. FIG. 2 shows a cross-sectional view of the second transistor.
[0134] The first transistor shown in FIG. 1 is formed on a p-type semiconductor substrate 1 and has a pair of n transistors respectively constituting a source or a drain. + Diffusion layer 2, and as n - LDD region 3 of the diffusion layer. no + Diffusion layer 2 may not be formed on p-type semiconductor substrate 1 but may be formed in a p-type well. On the semiconductor substrate 1 , there is a gate electrode 6 formed of a polysilicon film with a gate insulating film 5 interposed therebetween. Sidewall spacers 7 are formed on side end surfaces on both sides of the gate electrode 6 . The sidewall spacers 7 on both sides have substantially the same width.
[0135] Covering the gate electrode 6, the side wall isolation layer 7, and the n + An insulating silicide bulk f...
Embodiment approach 2
[0168] The solid-state imaging device according to Embodiment 2 will be described with reference to FIG. 7 showing a cross-sectional view of the first transistor. The solid-state imaging device of Embodiment 2 is the same as the solid-state imaging device of Embodiment 1 except that the configuration of the first transistor is different. Therefore, the same reference numerals are assigned to the same constituent elements as those in Embodiment 1, and repeated descriptions are omitted. The second transistor is the same as that shown in FIG. 2 .
[0169] The first transistor of this embodiment is limited by the silicide block film 16 so that the n on one side (right side) + The edge spacing D11 between the metal silicide layer 4a on the diffusion layer 2 and the gate electrode 15 is larger than n on the other side (left side). + The edge distance D12 between the metal silicide layer 4b on the diffusion layer 2 and the gate electrode 15 is large. form the side of the larger ed...
Embodiment approach 3
[0179] The solid-state imaging device according to Embodiment 3 will be described with reference to FIG. 8 showing a cross-sectional view of the first transistor. The solid-state imaging device of Embodiment 3 is the same as the solid-state imaging device of Embodiment 1 except for the configuration of the first transistor. Therefore, the same reference numerals are assigned to the same constituent elements as those in Embodiment 1, and repeated description is omitted, and only different parts will be described in detail. The second transistor is the same as that shown in FIG. 2 .
[0180] The first transistor of the present embodiment is limited by the sidewall spacer 18 having a larger width than the sidewall spacer of the second transistor, so that the edge distance D13 between the gate electrode 17 and the metal silicide layer 4 is wider than that of the gate of the second transistor. The edge spacing between the electrodes and the metal silicide layer is large.
[0181]...
PUM
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