Power-on circuit

Abstract

A power-on circuit which may generate a power-on signal that is insensitive to the rising speed of an I / O voltage or core voltage. A power-on signal may be generated according to current drive capabilities of NMOS and PMOS transistors based on the I / O voltage or core voltage. A power-on circuit may control an I / O voltage when the level of a core voltage is lower than the I / O voltage.

Description

[0001] This application claims the benefit of Korean Patent Application No. 10-2006-0088445 filed September 13, 2006, the entire contents of which are incorporated herein by reference. technical field [0002] The present invention relates to a power-on circuit, and more particularly, to a method for generating power-on circuits independent of I / O voltage or core voltage based on the current drive capability of NMOS and PMOS transistors based on I / O voltage or core voltage. The rate of rise of the core voltage affects the energization signal of the energization circuit. Background technique [0003] A semiconductor chip may go through a series of initialization procedures when it starts up, including applying an external voltage to the semiconductor chip. During startup, since the state of the input / output (I / O) terminals of the chip is unknown, the Retention Programmable Input Output (ORPIO) scheme can be used to avoid having data with another system connected to the chip. ...

AI Technical Summary

Problems solved by technology

[0004] However, when the I / O voltage and chip internal voltage (hereinafter referred to as "core voltage") are used independently in the RPIO scheme, a power-on circuit (POC) may be required

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