Forward looking branch target address caching

Abstract

A pipelined processor comprises an instruction cache (iCache), a branch target address cache (BTAC), and processing stages, including a stage to fetch from the iCache and the BTAC. To compensate for the number of cycles needed to fetch a branch target address from the BTAC, the fetch from the BTAC leads the fetch of a branch instruction from the iCache by an amount related to the cycles needed to fetch from the BTAC. Disclosed examples either decrement a write address of the BTAC or increment a fetch address of the BTAC, by an amount essentially corresponding to one less than the cycles needed for a BTAC fetch.

Description

technical field [0001] The teachings of this disclosure relate to techniques for caching branch instruction target addresses, particularly by prefetching cached target addresses relative to fetching cached branch instructions, and to processors using such techniques. Background technique [0002] Modern microprocessors and other programmable processor circuits often rely on pipeline processing architectures to improve execution speed. A pipelined processor includes multiple processing stages for sequentially processing each instruction as it moves through the pipeline. While one stage is processing an instruction, other stages along the pipeline are processing other instructions concurrently. [0003] Each stage of the pipeline performs a different function necessary for the overall processing of each program instruction. A typical simple pipeline includes an instruction fetch stage, an instruction decode stage, a memory access or read stage, an instruction execute stage, ...

AI Technical Summary

Problems solved by technology

The abandonment causes latency and reduces the benefit of the BTAC cache

Performance degradation increases as number of cycles required for BTAC extraction increases

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