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Multithreaded processor

A technology of multi-threaded processor and arithmetic unit, applied in multi-programming devices, electrical digital data processing, instruments, etc., can solve the problems of additional hardware, sound skipping, sound processing can not keep up, etc., and achieve accurate processing time. Effect

Inactive Publication Date: 2008-05-14
PANASONIC CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] The problem with the method of installing dedicated hardware is that although high-performance processing can be realized, if more functions need to be realized, the circuit scale will increase
Moreover, there is also a problem that additional hardware is required when adding new functions.
On the other hand, there is a problem in the method of media processing realized by using software that its performance is lower than that of the method equipped with dedicated hardware
[0008] However, with the method of media processing realized by using a multithreaded processor, there is a problem in distributing performance to multiple programs
[0009] Specifically, there is a problem that, since the time allocated to the video processing thread and the audio processing thread is insufficient, the video processing and audio processing cannot keep up, resulting in empty frames of the video, sound skipping of the audio, etc.

Method used

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Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0036] FIG. 1 is a block diagram showing the configuration of a multi-thread processor according to Embodiment 1 of the present invention.

[0037] A multi-threaded processor is a processor that independently executes N (N is an integer above 2) instruction streams (N threads) at the same time, including: instruction memory 101; instruction decoder 102; instruction scheduler 103; N N instruction buffers (the first instruction buffer 104, the second instruction buffer 105, ..., the Nth instruction buffer 106); N register files (the first register file 107, the second register file 108, ..., The Nth register file 109 ); the priority determination unit 110 ; the issue command determination unit 111 ; the computing unit group 112 ; and the write-back bus 113 .

[0038] The instruction memory 101 is a kind of memory, which stores the instructions executed by the multi-thread processor, and stores N instruction streams (threads) executed independently.

[0039] The instruction deco...

Embodiment 2

[0088] Next, a multi-thread processor according to Embodiment 2 of the present invention will be described.

[0089] The multi-thread processor according to the second embodiment has the same configuration as the multi-thread processor according to the first embodiment shown in FIG. 1 , but the priority determination unit 110 and the issue command determination unit 111 are different. Hereinafter, the multithreaded processor according to the second embodiment will be described centering on the priority determination unit and the issue instruction determination unit.

[0090] FIG. 7 is a diagram for explaining the configuration and operation of the priority determination unit 701 and the issue command determination unit 702 according to the second embodiment.

[0091] The priority determination unit 701 is provided instead of the priority determination unit 110 in the multithreaded processor shown in FIG. stream priority, and output priority information 707 indicating the prio...

Embodiment approach 3

[0105] Next, a multi-thread processor according to Embodiment 3 of the present invention will be described.

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Abstract

Provided is a multithreaded processor that can accurately estimate processing time necessary for each thread, and a multithreaded processor that simultaneously executes instruction streams, the multithreaded processor including: a computing unit group that executes instructions; an instruction scheduler that groups the instructions into groups for each of the instruction streams, the instructions being included in the each of instruction streams, and each of the groups being made up of instructions among the instructions to be simultaneously issued to the computing units; an instruction buffer which holds the instructions for each of the groups grouped by the instruction scheduler, the instructions being included in the each of instruction streams; and an issued instruction determining unit that reads the instructions for each of the groups from the instruction buffer in each of execution cycles of the multithreaded processor, and that issues the read instructions to the computing unit group.

Description

technical field [0001] The present invention relates to a multi-thread processor, which efficiently uses a plurality of computing units by issuing instructions of a plurality of instruction streams in parallel. Background technique [0002] Media processing such as compression and expansion of digitized video data, audio data, etc. requires a huge amount of computation. Therefore, dedicated hardware for media processing, high-performance DSP (Digital Signal Processor: Digital Signal Processor), and the like are spreading. [0003] Many standards such as MPEG (Moving Picture Experts Group) 2, MPEG4, H.263, and H.264 have already been put into practical use in these media processing. Therefore, digital AV (Audio-Visual: Video Audio) equipment is required to support media processing of multiple standards. Furthermore, there is a tendency that each media processing application program becomes more and more complex, the size of images, the number of audio channels, etc. increas...

Claims

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Application Information

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IPC IPC(8): G06F9/38H04N7/26G06F9/46G06F9/48
CPCG06F9/3802G06F9/3814G06F9/3851G06F9/3885
Inventor 森下广之尾崎伸治山本崇夫中岛雅逸
Owner PANASONIC CORP
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