Descriptor prefetch mechanism for high latency and out of order DMA device

A technology for moving and accessing devices of blocks, applied in the field of direct memory access controllers

Active Publication Date: 2008-07-16
MELEROS TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The size of the descriptor prefetch buffer holds an appropriate number of descriptors for a given latency environment

Method used

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  • Descriptor prefetch mechanism for high latency and out of order DMA device
  • Descriptor prefetch mechanism for high latency and out of order DMA device
  • Descriptor prefetch mechanism for high latency and out of order DMA device

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Embodiment Construction

[0032] Referring now to the drawings, and with particular reference to FIGS. 1-2 , exemplary diagrams of data processing environments in which illustrative embodiments of the invention may be implemented are provided. It should be understood that Figures 1-2 are exemplary only, and are not meant to assert or imply any limitation as to the environments in which aspects or embodiments of the present invention may be practiced. Many modifications to the described environments may be made without departing from the spirit and scope of the invention.

[0033] 1 is an exemplary block diagram of a data processing system in which aspects of the illustrative embodiments may be implemented. The exemplary data processing system shown in FIG. 1 is an example of a cell broadband engine (CBE) data processing system. While CBE will be used in the description of the preferred embodiments of the invention, the invention is not limited thereto, as will become apparent to those of ordinary skil...

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Abstract

A DMA device prefetches descriptors into a descriptor prefetch buffer. The descriptor prefetch buffer is sized to hold an appropriate number of descriptors for a given latency environment. To support linked lists of descriptors, the DMA engine prefetches descriptors based on the assumption that the descriptors are in order in memory, and any descriptors found to violate this assumption are discarded. The DMA engine tries to keep the descriptor prefetch buffer full by requesting multiple descriptors per transaction whenever possible. The bus engine reads these descriptors from system memory and writes them to the prefetch buffer. The DMA engine can also use aggressive prefetching, where the bus engine requests the maximum number of descriptors that the buffer will support whenever there is any room in the descriptor prefetch buffer. The DMA device discards any remaining descriptors that cannot be stored.

Description

technical field [0001] The present invention generally relates to improved data processing systems and methods. More specifically, the present invention relates to direct memory access controllers that support high latency devices. Background technique [0002] Many system-on-a-chip (SOC) designs include devices known as direct memory access (DMA) controllers. The purpose of DMA is to efficiently move blocks of data from one location in memory to another. DMA controllers are commonly used to move data between system memory and input / output (I / O) devices, but are also used to move data between one area in system memory and another. The DMA controller is called "direct" because the processor is not involved in moving data. [0003] In the absence of a DMA controller, blocks of data can be moved by having the processor copy data from one memory space to another slice-by-slice under software control. This is usually not ideal for larger data blocks. When a processor copies ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F13/28
CPCG06F13/28
Inventor R·尼古拉斯B·C·德雷鲁普J·古普塔G·比朗L·E·德 拉 托雷
Owner MELEROS TECH CO LTD
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