Squarer circuit and implementing method thereof

An implementation method, a squarer technology, which can be applied to instruments, devices that perform computing operations by changing electricity or magnetic quantities, analog computers, etc., and can solve serious problems such as waste of resources and so on.

Inactive Publication Date: 2008-12-10
HUAWEI DEVICE CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0018] In the process of realizing the present invention, the inventor found that the above prior art has the following disadvantages: the waste of resources in the methods in the prior art is relatively serious

Method used

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  • Squarer circuit and implementing method thereof
  • Squarer circuit and implementing method thereof
  • Squarer circuit and implementing method thereof

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Embodiment Construction

[0029] Below in conjunction with accompanying drawing and embodiment, the specific embodiment of the present invention is described in further detail:

[0030] Embodiment 1 of the present invention provides an implementation circuit of a 4-bit signed number squarer, and the binary expression of the 4-bit signed number is:

[0031] A=a 3 ×2 3 +a 2 ×2 2 +a 1 ×2 1 +a 0 ×2 0 ,

[0032] where a i =0 or 1, i=0,1,2,3;

[0033] Such as image 3 As shown, the circuit includes: an acquisition module 310 , a first summing module 320 , a second summing module 330 , a third summing module 340 , and a combining module 350 .

[0034] Wherein, the obtaining module 310 is used to obtain the mutual multiplication term, self-multiplication term and supplementary term occurring in the square process according to the input data, and the input terminal is the value of each digit of a 4bit signed number: a 3 、a 2 、a 1 、a 0 , the output terminal is the mutual multiplication term, self ...

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Abstract

The invention discloses a realization circuit for a squarer, which comprises: an acquisition module that is used to acquire a mutual multiply item, square item and supplement item according to the input symbolic number during the squaring process; a first sum module that sums up the mutual multiply item attained by the acquisition module and generates a first sum result; a second sum module that sums up the first sum result attained by the first sum module and the square item attained by the acquisition module and generates a second sum result; a third sum module that sums up the second sum result attained by the second sum module and the supplement item attained by the acquisition module and generates a third sum result; a combination module that combines the third sum result attained by the third sum module and a lower 2bit digit and generates a square result for the symbolic number. Therefore, the invention simplifies the circuit structure for realizing the squarer and greatly saves the circuit resources.

Description

technical field [0001] The embodiments of the present invention relate to the field of circuit design, in particular to a squarer circuit and an implementation method. Background technique [0002] The squarer is one of the typical circuits widely used in the field of science and technology. In actual circuit design, the squarer can be realized by a multiplier or by a look-up table method. [0003] Among them, the implementation structure using the multiplier is as follows figure 1 As shown, it includes an absolute value implementation circuit and a multiplier. The implementation process of the squarer is as follows, and the 4bit signed number is used as an example to illustrate. [0004] First, the binary expression of the input data A of 4bit signed number is as follows: [0005] A=a 3 ×2 3 +a 2 ×2 2 +a 1 ×2 1 +a 0 ×2 0 , [0006] where a i =0 or 1, i=0,1,2,3; [0007] Step 1: Use the absolute value implementation circuit to obtain and output the absolute valu...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06G7/20
Inventor 魏昊
Owner HUAWEI DEVICE CO LTD
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