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Memory address arranging method

A memory address, memory technology, applied in memory address/allocation/relocation, instruments, static indicators, etc., can solve the problem of insufficient memory, and achieve the effect of flexible reading and writing

Inactive Publication Date: 2009-01-14
NOVATEK MICROELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, if due to hardware configuration requirements, such as a rotatable panel design, the memory is connected to a source driver on the horizontal panel and connected to another source driver on the vertical panel when using another function, so it must be able to simultaneously Reading and writing multiple horizontal data and simultaneously reading and writing multiple vertical data, the memory of the previous technology is not enough

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no. 3 example

[0069] In the third embodiment, it is required to continuously read and write 2 pieces of data horizontally or vertically to a memory connected to a display panel. image 3 The display panel 300 is shown, and data addresses A to Z and 1 to 6 represent addresses of display pixels. Figure 9 shown corresponding to image 3 A related schematic diagram after address conversion of the memory 900 of the display panel. Among them, the sub-blocks 901 and 902 are two sub-blocks cut horizontally, and there are data converters 903, 904, the left end control signal 905 and the right end control signal 906. Data; 909 and 910 are the data of the read sub-blocks 901 and 902, respectively. The signal 911 is the Y[0] value, besides controlling the data converters 903 and 904 , it also controls the X[0] value of the right side control signal 906 . Data addresses A~Z and addresses 1~6 are the addresses after internal translation of the memory, and the brackets represent the X and Y axis value...

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Abstract

The invention discloses a storage address set-up method; the method comprises the following steps of utilizing operation units divided by translating data of different ordinates to different abscissa or operation units divided by translating data of different abscissa to different ordinates so as to realize the function of simultaneously reading and writing multiple data longitudinally and transversely and avoid the restriction that multiple data can only be transversely or longitudinally written or read simultaneously.

Description

technical field [0001] The invention relates to a method for address arrangement, and in particular to a memory address arrangement method. Background technique [0002] Technology is changing with each passing day. In order to store large amounts of data, memory is developing towards larger capacity and faster access speed, which is the trend of the times. The larger the memory capacity, the higher the access speed. The faster the speed, the higher the frequency of writing and reading; as we all know, the operation of the memory is mainly based on writing and reading, and the frequency of writing and reading is determine its operating frequency. Therefore, the operating frequency of a large-capacity memory is often too high to be lowered, which also limits the minimum operating frequency of the system, which brings higher restrictions or requirements on the configuration of other software and hardware in the system. Therefore, how to maintain or even increase the access s...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F12/06G09G3/36
Inventor 刘上逸
Owner NOVATEK MICROELECTRONICS CORP