Low voltage differential signal receiver circuit

Abstract

The invention provides a low voltage differential signal receiver circuit, which comprises a pair of differential input transistors, a pair of control transistors, a current mirror load circuit, a first feedback reverser and a second feedback reverser, wherein the first feedback reverser, the second feedback reverser and the pair of control transistors form a negative feedback path. The change ofthe value of the input voltage of the first feedback reverser is suppressed and the value of the input voltage of the first feedback reverser is kept around a threshold voltage of the first feedback reverser.

Description

technical field [0001] The present invention relates to a low voltage differential signal (LVDS) receiver circuit, and more particularly, to a low voltage differential signal receiver circuit which has a simple structure but can obtain a large voltage gain. Background technique [0002] LVDS technology is generally used to provide low power and low voltage to other high-speed input and output interfaces, especially for point-to-point transmission, such as network equipment in data and communication networks. The general practice is that LVDS is equipped in an integrated circuit to overcome the defects of the previous stage I / O interface circuit. When the differential input voltage of the LVDS receiver is small (about 100mV to 200mV), and the switching speed of the input signal is high (about 400MHz), the following issues must be considered in the production of the LVDS receiver. First, the circuit must have sufficient voltage gain. Second, the circuit must convert a differ...

AI Technical Summary

Problems solved by technology

First, the circuit must have sufficient voltage gain

Second, the circuit must convert a differential output voltage into a single output voltage

Third, the circuit must convert a single output voltage into a standard logic level

Fourth, the amplifier circuit must be relatively simple to achieve high switching speed

Although this prior art comparator 20 satisfies the second requirement of an LVDS receiver, it requires an additional bias voltage VBB which will not be easily achievable under various input voltages and process variations

[0005] U.S. Patent No. 5,764,086 discloses a circuit with a large common mode range and a large voltage gain, but it is too complicated to realize, and its speed is too slow

In "A 250Mb / s / pin 1Gb Doudle Data Rate SDRAM with a Bi-Directional Delay and an Inter-Bank Shared RedundancyScheme" published by Y.Takai and others in NEC Corp.ISSCC99 WP24.5, pages 418 to 419, it is revealed that A circuit that has a large common-mode range and does not require any reference voltage, but its gain and speed are still not good enough

[0006] Although it is possible to combine these two circuits to implement an LVDS receiver, it will be too complex to meet the requirements of LVDS receiver in terms of speed, stability and dynamic range

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