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Chemical mechanical polishing slurry compositions, methods of preparing the same and methods of using the same

A chemical-mechanical and compositional technology, applied in the direction of polishing compositions containing abrasives, chemical instruments and methods, non-ionic surface active compounds, etc., can solve problems such as deterioration of electrical characteristics and contact characteristics, polysilicon line height difference, etc.

Active Publication Date: 2012-07-11
CHEIL IND INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, this polishing selectivity can lead to dishing of the polysilicon film due to chemomechanical effects.
Dishing can adversely affect subsequent photoprocessing, which can lead to height differences in the formed polycrystalline silicon lines
Results in deterioration of electrical characteristics and contact characteristics within the unit

Method used

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  • Chemical mechanical polishing slurry compositions, methods of preparing the same and methods of using the same
  • Chemical mechanical polishing slurry compositions, methods of preparing the same and methods of using the same
  • Chemical mechanical polishing slurry compositions, methods of preparing the same and methods of using the same

Examples

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specific Embodiment approach

[0057] The present invention will be described in more detail with reference to the following examples. However, these examples are given for illustrative purposes and are not to be construed as limiting the scope of the invention.

Embodiment 1

[0060] First, 12.5 g of an aqueous solution of 20 wt % tetramethylammonium hydroxide (TMAH) was added to 4111.9 g of ultrapure water. 10 minutes after the addition, 0.1 g of polyoxyethylene perfluorobutylsulfonyl ester and 0.5 g of the compound represented by Formula 3 were added thereto.

[0061]

[0062] This mixture was mixed with 875 g of a 20% by weight aqueous solution of colloidal silicon dioxide in a reactor. The resulting mixture was agitated at 500 rpm and filtered through a 5 micron filter to obtain a slurry. The wafer was polished with this slurry for one minute under the following conditions: Polishing machine: MIRRA (AMAT); Polishing pad: IC1010 / Suba IV K groove (Rhom & Haas); Polishing substrate: Poly-Si, PTEOS, 8" Blank wafer; disk speed: 120rpm; head speed: 115rpm; pressure: 2.0psi; In-wafer non-uniformity (WIWNU) outside 3 mm of the edge was evaluated. The results are shown in Table 1 below.

Embodiment 2

[0064] A slurry was obtained in the same manner as in Example 1 except that 1.0 g of the compound represented by Formula 3 was added. The polishing performance of the slurries was evaluated according to the procedure described in Example 1. The results are shown in Table 1 below.

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Abstract

Provided herein are chemical mechanical polishing (CMP) slurries and methods for producing the same. Embodiments of the invention include CMP slurries that include (a) a metal oxide; (b) a pH-adjusting agent; (c) a fluorinated surfactant; and (d) a quaternary ammonium surfactant. In some embodiments, the fluorinated surfactant is a non-ionic perfluoroalkyl sulfonyl compound. Also provided herein are methods of polishing a polycrystalline silicon surface, including providing a slurry composition according to an embodiment of the invention to a polycrystalline silicon surface and performing a CMP process to polish the polycrystalline silicon surface.

Description

technical field [0001] The present invention relates to chemical mechanical polishing (CMP) slurry compositions, and more particularly, to CMP slurry compositions for polishing polysilicon surfaces. The invention also relates to methods of preparing CMP slurry compositions and methods of polishing polysilicon surfaces. Background technique [0002] Ultra-large-scale integration (ULSI) in integrated circuit technology represented by 512M-bit and 1G-bit dynamic random access memory (DRAM) can be realized by high-performance and highly integrated semiconductor devices. Therefore, relatively small line widths (eg, 55 to 60 nm) can be formed in the fabrication of next-generation devices as the minimum process dimensions required to fabricate these devices further shrink. [0003] Integration in integrated circuits leads to a reduction in the size of semiconductor devices and requires multilayer interconnections. Highly integrated semiconductors can be fabricated by repeatedly a...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): C09K3/14
CPCC09K3/1463C09G1/02H01L21/3212C09K3/1454H01L21/30625C11D1/66C01F7/02C01G25/02
Inventor 郑载薰李仁庆
Owner CHEIL IND INC