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Difference input signal receiving circuit

A technology of signal reception and differential input, applied in differential amplifiers, logic circuit connection/interface layout, logic circuit coupling/interface using field effect transistors, etc. Effects of reduced transfer rate, stable hysteresis voltage, and high transfer rate

Inactive Publication Date: 2011-05-04
NO 24 RES INST OF CETC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Its disadvantage is that the working speed of the circuit is not high due to the introduction of positive feedback. Under the standard 0.35μm CMOS process conditions, the highest transmission rate of this circuit structure is 1.6Gb / s, which cannot meet the current high-speed D / A conversion. device requirements

Method used

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Embodiment Construction

[0022] The specific implementation manners of the present invention are not limited to the following description, and are now further described in conjunction with the accompanying drawings.

[0023] The differential input signal receiving circuit implemented in the present invention is as follows: figure 2 shown. It consists of a basic amplifying circuit unit and a hysteresis voltage generating circuit unit. The basic amplifier circuit unit includes: PMOS transistor MP1, PMOS transistor MP2, NMOS transistor MN1, NMOS transistor MN2, and PMOS transistor MP10 used as the first-stage amplifier circuit. Initial amplification; and NMOS tube MN3, NMOS tube MN4, PMOS tube MP7, PMOS tube MP8 used as the second-stage amplifier circuit, this stage circuit further amplifies the signal; and NMOS tube MN5, NMOS tube MN6 used as the bias current generating circuit , PMOS tube MP9, this stage circuit provides bias current I for the differential input stage circuit through MP10 bias , I ...

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Abstract

The invention relates to a difference input signal receiving circuit, comprising a basic amplifying circuit unit and a retarding voltage generating circuit unit. In the invention, the circuit is addedwith two PMOS tubes of MP5 and MP6 based on a custom circuit, a retarding voltage can be obtained by a method for leading in input offset by two the PMOS tubes, and stable retarding voltage can be obtained without leading in partial positive feedback. The circuit has the advantages of stable retarding voltage and high transmission speed, and the transmission speed of the difference input signal receiving circuit can be increased to 2.4 Gb / s from 1.6 Gb / s of the custom circuit. The circuit can be widely applied to the field of high-speed D / A converters.

Description

technical field [0001] The invention relates to a differential input signal receiving circuit, in particular to a differential input signal receiving circuit for a high-speed D / A converter. Its direct application field is high-speed D / A converter. Background technique [0002] In recent years, with the increasing performance of D / A converters, the requirements for its interface circuits are getting higher and higher. Low-voltage differential signal (LVDS) receiving technology is due to its fast transmission speed, small signal swing, low power consumption, and electromagnetic It has the advantages of small interference and strong anti-interference ability, and is widely used in high-speed and high-performance D / A converters. [0003] Typical conventional low-voltage differential signal receiving circuits such as figure 1 shown. It detects the input signal through a Schmitt trigger composed of P1, P2, N1, N2, N8, and N9, and ensures a hysteresis voltage of 25mV to 50mV. I...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03F3/45H03K19/0185H03M1/66
Inventor 黄兴发沈晓峰李梁苏晨李儒章何开全
Owner NO 24 RES INST OF CETC