Peripheral shading mask structure used for manufacturing semiconductor wafer and manufacturing method thereof

Abstract

The invention discloses a method for manufacturing a peripheral shading mask structure used for manufacturing a semiconductor wafer. The method comprises the following steps: providing a substrate which comprises an opaque layer covering the substrate, a covered negative photoresist layer, a stop layer covering the negative photoresist layer and a positive photoresist layer covering the stop layer; patterning the positive photoresist layer to form one or more windows in the positive photoresist layer; removing the exposed stop layer in the one or more windows, exposing a part of negative photoresist layer and patterning the negative photoresist layer of the exposed part; developing the negative photoresist layer of the exposed part, removing the opaque layer of the exposed part, and exposing the lower partial substrate; and removing the negative photoresist layer, the stop layer and the positive photoresist layer of any residual part, and providing a patterned mask. The patterned maskis used for manufacturing an integrated circuit. The invention also provides the peripheral shading mask structure used for manufacturing the semiconductor wafer.

Description

technical field [0001] The present invention relates to integrated circuits and their processes for the manufacture of semiconductor devices. More specifically, the present invention provides a method of fabricating masks for the manufacture of advanced integrated circuits, such as dynamic random access memory devices, static random access memory devices (SRAMs), application specific integrated circuit devices (ASICs) , microprocessors and microcontrollers, flash memory devices, and other devices. Background technique [0002] Integrated circuits, or "ICs," have grown from hundreds of interconnected devices fabricated on a single silicon chip to millions of devices. Current ICs offer performance and complexity far beyond what was originally imagined. To enable increases in complexity and circuit density (e.g., the number of devices that can fit on a given chip area), the minimum device feature size, also known as the device "geometry," has increased with each IC generation...

AI Technical Summary

Problems solved by technology

Although negative photoresists perform better than positive photoresists, the process time will be much longer

Typically, 30 to 60 percent of the negative photoresist is exposed, which further increases process time

Also, the existing process looks cumbersome and causes quality problems in the mask itself

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