High speed synchronization technique of character and figure sequence

Abstract

The invention relates to a high speed synchronization technique of character and figure sequence used for detecting bit error, comprising the following steps: writing the set character and figure data into a programmable figure and character storage unit, namely a static random access memory (SRAM), by a CPU; then switching to an address generator to control the SRAM to read the character data in a circulation manner; and carrying out buffer and displacement processing on the read-out characters and sending to a synchronous judging circuit to perform synchronous judgment with the received character data, wherein if the received characters are different from the local characters, then sending out a stop signal, prohibiting the address generator to generate new addresses and maintaining to compare the local character read by the previous address with the next received character coming continuously; and if the received characters are identical to the local characters, then allowing the address generator to generate new addresses and carrying out displacement processing on the read-out data and comparing in sequence; and when the same characters are greater than the synchronous threshold, then carrying out synchronization on the received character and figure and the local character and figure. The invention provides a high speed synchronization technique of character and figure sequence which is reliable and economical and is used for detecting bit error.

Description

technical field [0001] The invention relates to a high-speed word pattern sequence synchronization technology for bit error code detection. Background technique [0002] With the improvement of the complexity and transmission speed of the data transmission system, the length of the programmable word pattern sequence used for testing the transmission equipment is required to be longer and the generation rate is higher and higher, so as to fully meet the requirements of evaluating the performance of the equipment. At present, the length of programmable word graphics can reach several megabits, and the graphics rate can reach GHz, but the processing speed of the memory used to store graphics can hardly reach the rate of GHz, and with the increase of speed and capacity, the cost of memory is also rapidly Improvement, the conventional circuit method is difficult to meet the design requirements. Contents of the invention [0003] The purpose of the present invention is to provi...

AI Technical Summary

Problems solved by technology

At present, the length of programmable word graphics can reach several megabits, and the graphics rate can reach GHz, but the processing speed of the memory used to store graphics can hardly reach the rate of GHz, and with the increase of speed and capacity, the cost of memory is also rapidly Improvement, the conventional circuit method is difficult to meet the design requirements

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