Unlock instant, AI-driven research and patent intelligence for your innovation.

Chip layout structure and method

A layout structure and layout method technology, applied in the direction of electrical components, electrical solid devices, circuits, etc., can solve the problems of increasing manufacturing costs

Active Publication Date: 2010-10-20
IND TECH RES INST
View PDF0 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Furthermore, the redesign of the RDL represents an increase in manufacturing costs

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Chip layout structure and method
  • Chip layout structure and method
  • Chip layout structure and method

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0032] In order to make the above-mentioned features and advantages more comprehensible, exemplary embodiments will be exemplified below and described in detail with accompanying drawings.

[0033] Figure 1A A schematic diagram of a chip layout structure of an exemplary embodiment is shown. Figure 1B draw Figure 1A A partially enlarged perspective view of . refer to Figure 1A and Figure 1B The chip layout structure 100 includes a first conductive via 109 and a second conductive via 110 , wherein the conductive vias 109 and 110 penetrate through the chip 115 . In this embodiment example, the conductive vias 109 and 110 can be through silicon vias (Through Silicon Via, TSV), forming a double-strand through silicon via (Twisted TSV) device structure. The conductive via 109 includes a first contact 101 and a second contact 105 , and the above two contacts are respectively located on the upper and lower sides of the chip 115 . In addition, the contact 101 and the contact 10...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention relates to a chip layout structure and a method. The chip layout structure comprises a first conductive through hole, a second conductive through hole, a chip and eight joints. The first conductive through hole and the second conductive through hole pass through the chip, wherein the first conductive through hole comprises a first joint and a second joint; the second conductive through hole comprises a third joint and a fourth joint; a fifth joint is communicated with the third joint; a sixth joint is communicated with the second joint; a seventh joint is communicated with the first joint; the eighth joint is communicated with the fourth joint; and on the vertical direction of the chip, the first joint is partially or completely superposed with the second joint, the third joint is partially or completely superposed with the fourth joint, the sixth joint is partially or completely superposed with the fifth joint, and the eighth joint is partially or completely superposed with the seventh joint.

Description

technical field [0001] The invention relates to a chip layout structure and method, in particular to a stack chip layout structure and method. Background technique [0002] At present, the technology of manufacturing transistors on a single chip is under development. By laying out stacked chips in the vertical direction, chips with different functions or different process technologies can be integrated to solve the difficulty of integrating different functions or different types of transistors into a single chip. . However, the current layout of signal wiring in stacked chips is to use redistribution layer technology (Redistribution Layer, RDL) winding on the front or back of the chip to change the position of the signal contacts, and then use micro bumps (Micro Bump) to make stacking bonding between chips. Accordingly, signals between multiple chips can be sequentially transmitted up and down through the windings, contacts, micro-bumps, and through-silicon vias (TSVs). ...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Applications(China)
IPC IPC(8): H01L23/48H01L23/52H01L25/00H01L21/60
CPCH01L24/16H01L2224/16H01L2924/00012
Inventor 周永发蒯定明
Owner IND TECH RES INST