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Chip packaging structure

A chip packaging structure and chip technology, applied in the direction of electrical components, electric solid devices, circuits, etc., can solve the problems of increasing mold costs and achieve the effect of reducing mold costs

Active Publication Date: 2012-07-04
ADVANCED SEMICON ENG INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] However, since the encapsulant 160 needs to have the cavity 162, it is necessary to use a specially designed mold to form the encapsulant 160, which will increase the cost of the mold.

Method used

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Experimental program
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Embodiment Construction

[0023] figure 2 A schematic cross-sectional view of a chip package structure according to an embodiment of the present invention is shown. Please refer to figure 2 , the chip packaging structure 200 of this embodiment includes a first substrate 210, a chip 220, a second substrate 230, a third substrate 240, a plurality of conductive bumps 250, a plurality of first wires 260 and an encapsulant 270 .

[0024] The chip 220 is disposed on the first substrate 210 and is electrically connected to the first substrate 210 . The first substrate 210 is, for example, a carrying circuit board. Specifically, the chip 220 can be electrically connected to the first substrate 210 by a plurality of second wires 280 , wherein two ends of each second wire 280 are respectively connected to the chip 220 and the first substrate 210 . In addition, the chip 220 can be electrically connected to the outside by a plurality of solder balls 290 disposed on the first substrate 210 , wherein the solder...

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Abstract

The invention discloses a chip packaging structure, comprising a first substrate, a chip, a second substrate, a third substrate, a plurality of electrically conductive protrusions, a plurality of leads and a packaging colloid. The chip is configured on the first substrate. The second substrate is configured on the chip and includes a lead joint face towards the direction away from the chip. The third substrate is configured on the second substrate and includes a solder ball mounting face towards the direction away from the chip. The electrically conductive protrusions are configured between the second substrate and the third substrate so as to electrically connect the second substrate with the third substrate. The second substrate is connected with the first substrate via the leads. The packaging colloid is configured on the first substrate, covers the chip, the leads, the second substrate and the third substrate, and is exposed from the solder ball mounting face of the third substrate.

Description

technical field [0001] The present invention relates to a chip packaging structure, and in particular to a chip packaging structure of stackable components. Background technique [0002] The purpose of chip packaging technology is to provide enough signal path, heat dissipation path and structural protection for the chip. The known technology proposes a package-on-package (POP) 3D packaging method, which can reduce the area occupied by these chip packaging structures on the circuit board by stacking multiple chip packaging structures on each other. [0003] figure 1 A schematic cross-sectional view of a known chip package structure applicable to package stacking is shown. Please refer to figure 1 A chip 110 of the chip package structure 100 is disposed on a first substrate 120 , and a second substrate 130 is disposed on the chip 110 . The second substrate 130 is electrically connected to the first substrate 120 by a plurality of first wires 140 , and the chip 110 is elec...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/12H01L23/48H01L23/31
CPCH01L2224/48091H01L2224/73265
Inventor 李玉麟
Owner ADVANCED SEMICON ENG INC