Method for optimizing domain of CMOS (Complementary Metal-Oxide-Semiconductor) image sensor as well as etching method

Abstract

The invention relates to a method for optimizing the domain of a CMOS (Complementary Metal-Oxide-Semiconductor) image sensor as well as an etching method. The etching method comprises the following steps of: providing a substrate, wherein a medium layer is formed on the surface of the substrate; forming a photoresist pattern on the surface of the medium layer; etching the medium layer by using the photoresist pattern as a mask until the medium layer with partial thickness is removed; executing a charge release process to the medium layer; and etching the remaining medium layer by using the photoresist pattern as the mask. The etching method of the invention can effectively protect the corners of the etched medium. The method for optimizing the domain of the CMOS image sensor can improve the packing factor of the CMOS image sensor and effectively improve the image quality of the CMOS image sensor.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a method for optimizing the layout of a CMOS image sensor and an etching method. Background technique [0002] At present, Charge Coupled Device (CCD) is the main practical solid-state image sensing device, which has the advantages of low read noise, large dynamic range, and high response sensitivity, but CCD has the disadvantages that are difficult to compete with mainstream complementary metal oxide semiconductor ( The disadvantage of Complementary-Metal-Oxide-Semiconductor (CMOS) technology compatibility is that it is difficult to achieve single-chip integration for image sensors based on charge-coupled devices. The CMOS image sensor (CMOS ImageSensor, CIS) can integrate the pixel array and peripheral circuits on the same chip because of the same CMOS technology. Compared with the charge-coupled device, the CMOS image sensor has small size, light weight, low power L...

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Problems solved by technology

Specifically, the effective width W of the transistor gate electrode region b13 of the pixel unit eff The gate electrode area width W of the transistor is smaller than the actual layout total , taking into account the above factors, the transistor gate electrode area width W of the actual layout total It will be enlarged accordingly in the design to meet the effective gate electrode area width W eff Practical requirements, but this actually limits the area of ​​the active region of the photodiode

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