On-line error correcting device for fault by parity check code and method thereof

A technology of parity check code and error correction device, which is applied in the field of online testing and can solve problems such as huge redundancy overhead.

Inactive Publication Date: 2011-04-27
HARBIN INST OF TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0007] The purpose of the present invention is to solve the problem that the redundant overhead caused by the existing online test of the embedded memory using the error correction code is too large, and provides an online fault correction device and method using the parity code

Method used

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  • On-line error correcting device for fault by parity check code and method thereof
  • On-line error correcting device for fault by parity check code and method thereof
  • On-line error correcting device for fault by parity check code and method thereof

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specific Embodiment approach 1

[0064] Specific implementation mode one: the following combination Figure 1 to Figure 3 Describe this embodiment mode, a kind of using parity check code to carry out fault online error correction device described in this embodiment mode, it comprises signal analyzer 1, controller 2, RAM memory 3, parity check code memory 4, new input data parity Encoder 5, stored data parity encoder 6, check code comparator 7, fault flag memory 8, data selector 9 and Hamming code error corrector 10,

[0065] The read-write control signal r_w and the address signal addr are sent to the signal analyzer 1, and the read-write control signal r_w is sent to the controller 2 and the data selector 9 at the same time, and the address signal addr is sent to the RAM memory 3, the parity checker at the same time Code memory 4, fault flag bit memory 8 and Hamming code error corrector 10,

[0066] The signal analyzer 1 outputs the new signal input flag signal_check to the controller 2, the controller 2 ou...

specific Embodiment approach 2

[0078]Specific Embodiment 2: Based on the online error correction method of a faulty online error correction device using parity codes described in Embodiment 1, it is characterized in that the method is divided into two parts: reading and writing.

[0079] The detection method during write operation includes the following steps:

[0080] Step 1, the signal analyzer 1 detects and analyzes whether there is a new write signal input,

[0081] If it is detected that there is a new write signal input, the signal analyzer 1 will output the new signal input flag signal_check=(100) B , and then perform step 2; if no new write signal input is detected, signal analyzer 1 identifies signal_check=(000) with its output new signal input B , continue to detect;

[0082] Step 2, the data selector 9 selects the new input data data_in as the output of the error data fault_data, and as the input of the Hamming code error corrector 10,

[0083] Step 3, controller 2 receives new signal input fl...

specific Embodiment approach 3

[0116] Specific embodiment three: this embodiment further explains embodiment two, the process that Hamming code encoder 10-7 encodes during writing operation is:

[0117] The input data is: a 0 a 1 …a k-1 , the Hamming code data is: H 0 h 1 …H k-1 ;

[0118] Step a, construct the parity check matrix H of the optimal odd-weight code:

[0119]

[0120] Each element h in check matrix H i，j =0 / 1, n is the codeword of the error correction code, k is the length of the information bit, and satisfies: nn-k -1;

[0121] Step b, calculate the check digit:

[0122] H 0 = a 0 · h 00 ⊕ a 1 · h 01 ⊕ . . . ⊕ a k - 1 · h 0 , ...

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Abstract

The invention relates to an on-line error correcting device for faults by parity check codes and a method thereof, belonging to the field of on-line test. The invention solves the problem of huge redundant cost when traditional error correcting codes are used for the on-line test for an embedded memory. The on-line error correcting device for faults comprises two processes of error detection and error correction, wherein the error detection comprises the following steps of: detecting whether new addresses are input or read-write signals are changed; calculating check codes for data; reading the data and comparing the data with memorized check codes; writing a compared result in a fault flag bit memory; and respectively writing fault addresses and the error correcting codes in corresponding memories. The process of the error correction comprises the following steps of: detecting whether the new addresses are input or the read-write signals are changed; judging fault flag bits; and searching the error correcting codes. By using the invention, the on-line test is carried out for the embedded memory under the condition that the memories are not changed to memorize data and the normal read-write operation of the memories is not influenced, and all the faults of odd numbers are detected.

Description

technical field [0001] The invention relates to an on-line fault correction device and method using a parity check code, which belongs to the field of on-line testing. Background technique [0002] Since the advent of integrated circuits, they have followed Moore's Law and developed at an astonishing speed. At present, integrated circuits have entered the era of ultra-deep submicron, integrated circuit electronic devices are getting smaller and smaller, and the chip scale is getting bigger and bigger. With the rapid improvement of integrated circuit technology, the design tools of integrated circuits have also made great leaps. Under the background of these technologies, hundreds of millions of transistors can be integrated on a single silicon chip, so that the complex system that can only be realized by the cooperation of multiple chips can be realized through a single chip. This kind of chip that replaces the original multiple chips to form a complex system with a single...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C29/42
Inventor 俞洋杨智明付宁李嘉铭乔立岩彭喜元
Owner HARBIN INST OF TECH
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