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Method for Determining Electromigration Lifetime of Interconnects

A method of determining and interconnecting wire technology, applied in the direction of single semiconductor device testing, etc., can solve the problem of unobtainable reliability life and so on

Active Publication Date: 2015-10-28
SHANGHAI INTEGRATED CIRCUIT RES & DEV CENT
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] In order to solve the existing technology, when formulating the reliability evaluation structure, the metal line width in the worst case is defined by experience or by referring to the structure of the process generation of other manufacturers, and the reliability life in the worst case cannot be obtained. Problem, the present invention provides a method for determining the electromigration lifetime of interconnection wires

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  • Method for Determining Electromigration Lifetime of Interconnects

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Embodiment Construction

[0017] In order to make the protection scope of the present invention clearer and the content of the invention easier to understand, the following introduces the preferred embodiments of the present invention.

[0018] The present invention tests the failure time of different structures of interconnection lines of each line width by measuring the interconnection line, and then uses the black equation to obtain the normalized life of at least three types of interconnection line widths, thereby fitting and obtaining the interconnection line electromigration The quadratic function relationship between the lifetime and the line width of the interconnection line, and then the electromigration lifetime of the interconnection line with any width can be obtained.

[0019] The present invention provides a method for determining the electromigration lifetime of an interconnection wire, specifically as follows:

[0020] Selecting at least three interconnect lines with different line widt...

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Abstract

The invention provides a method for determining electro-migration lifetime of interconnected lines, comprising the steps of: selecting at least three interconnected lines with different line widths; the at least three interconnected lines with different line widths are formed under a same determination technological condition; testing the failure times of different structures of each interconnected line and obtaining the average failure time corresponding to each interconnected line by utilizing statistic distribution; obtaining the normalized lifetime of each interconnected line according to black equation when temperature density and current density are determined; fitting to obtain secondary function relations between the normalized lifetimes and the line widths of the interconnected lines; and obtaining the electro-migration lifetime under the worst condition through curves corresponding to the secondary function relations so as to obtain the line widths corresponding to the electro-migration lifetime under the worst condition. By adopting the method provided by the invention, the electro-migration lifetime of the interconnected lines under the worst condition can be precisely evaluated and important information is provided for the technologies of metal development.

Description

technical field [0001] The invention relates to the field of semiconductor testing, in particular to a method for determining the electromigration lifetime of an interconnection line. Background technique [0002] The electromigration of metal interconnection lines is the main reliability problem in microelectronic devices. When the metal lines are energized, the metal atoms migrate under the push of electrons, resulting in short circuits or open circuits of metal lines. Therefore, metal electromigration is a reliable method for integrated circuits. One of the important contents of sexual assessment. The reliability evaluation of integrated circuits in the industry is performed according to the JEDEC standard. According to the requirements of the JEDEC standard, the electromigration of metal lines not only needs to evaluate the lines with the minimum line width stipulated by the design rules, but also needs to evaluate the lines with a width greater than the average grain si...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G01R31/26
Inventor 唐逸周伟任铮冯程程陶金龙陈寿面
Owner SHANGHAI INTEGRATED CIRCUIT RES & DEV CENT