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Method and device for supporting field programmable gate arrays (FPGA) to download data

A gate array and data technology, applied in the field of field programmable gate array FPGA and FPGA, to shorten the download time and avoid incomplete signals

Active Publication Date: 2011-09-28
ZTE CORP
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  • Summary
  • Abstract
  • Description
  • Claims
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AI Technical Summary

Problems solved by technology

[0005] The present invention provides a method, device and FPGA supporting multiple FPGAs to download data, so as to solve the technical problem of how to ensure signal integrity while shortening the time required for downloading data from multiple FPGAs

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  • Method and device for supporting field programmable gate arrays (FPGA) to download data
  • Method and device for supporting field programmable gate arrays (FPGA) to download data
  • Method and device for supporting field programmable gate arrays (FPGA) to download data

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Embodiment Construction

[0040] In order to make the purpose, technical solution and advantages of the present invention more clear, the embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings. It should be noted that, in the case of no conflict, the embodiments in the present application and the features in the embodiments can be combined arbitrarily with each other.

[0041] The present invention provides a kind of FPGA, and this FPGA can support a plurality of equipment Field Programmable Gate Arrays (FPGA) to download data, and this FPGA comprises: n are used to provide the first port of clock signal for described from FPGA, and n is greater than An integer of 1; n second ports for loading data from the FPGA; and a transmission module, used to use the n first ports to send the n data to the n through a dedicated clock signal transmission channel with each from the FPGA. transmitting the clock signal from the FPGAs; and transmitting the d...

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Abstract

The invention provides a method and a device for supporting a plurality of field programmable gate arrays (FPGA) to download data, and the FPGAs. The method comprises the following steps that: a master FPGA concurrently transmits clock signals and the data to n slave FPGAs, wherein n is an integer bigger than 1. By adoption of the technical scheme of the invention, the completeness of the signal can be guaranteed during the shortening of time required by data downloading of the plurality of slave FPGAs.

Description

technical field [0001] The invention relates to the field of field programmable gate array FPGA technology, in particular to a method, device and FPGA for supporting multiple field programmable gate arrays to download data. Background technique [0002] With the large number of applications of Field Programmable Gate Arrays (FPGAs), it is becoming more and more common to have multiple FPGAs on a single board. Among them, multiple slave FPGAs usually download data in series, taking the FPGA of the ALTERA stratix4 series as an example, such as figure 1 As shown, the external device provides the working clock to FPGA1 through the DCLK pin of the master device, and provides the download data to the master device FPGA1 through DATA0. After the master device FPGA1 downloads the data, it outputs a low level to the nCE pin of FPGA2 through the pin nCEO Signal. FPGA2 continues to obtain the working clock from the external device through DCLK, and obtains the download data from the ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F13/38G06F9/445
Inventor 张桢
Owner ZTE CORP
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