Fat tree type network-on-chip mapping method based on differential evolution and predatory search strategy

Abstract

The invention discloses a fat tree type network-on-chip mapping method based on a differential evolution and predatory search strategy, which comprises the following steps of: (1) initializing the current optimal mapping result and defining a plurality of peripheral solutions which use any one solution as a center to form a limit array in the solution space; (2) setting limit arrays R[0], R[1],..., R[T-1] with the limit total amount of T at the periphery of the current optimal mapping result and defining the current limit variable to be R[i]; (3) searching the periphery of the current limit variable R[i] by adopting a differential evolution method; if a better solution is found out, updating the current optimal mapping result and turning back to the step (2); otherwise, turning to the step (4); (4) updating the current limit variable i which is equal to i plus 1; if i is smaller than T-1, turning back to the step (3); and otherwise, outputting the current optimal mapping result. By using the method, the problem of local optimum is solved through adjustment of limitation, the network energy consumption is greatly reduced, the mapping running time is reduced and the mapping of a low-energy consumption and rapid large-scale IP (Internet Protocol) core in the fat tree type network on a chip can be realized.

Description

Technical field [0001] The invention belongs to the field of network technology, relates to a system-level chip design and a method for mapping an on-chip IP core to a network node, and is suitable for fast IP core mapping of a large-scale fat tree-on-chip network with low energy consumption. Background technique [0002] The system-on-chip SoC based on the bus architecture is an integrated circuit design method characterized by IP core multiplexing. These IP cores can be general-purpose processors, coprocessors, DSPs, application-oriented hardware, memory modules, input / output modules, and so on. With the development of transistor technology and the rapid growth of processor frequency, the number and complexity of IP cores in SoC continue to increase. The main problems facing the bus structure are: (1) Long interconnection lines. With the increase in the number of IP cores connected to the bus, the length of the bus will inevitably increase, which will cause trouble to the back...

AI Technical Summary

Problems solved by technology

With the development of transistor technology and the rapid increase of processor frequency, the number and complexity of IP cores in SoC continue to increase, and the main problems faced by the bus structure are as follows: (1) The problem of long interconnect lines

As the number of IP cores connected to the bus increases, the length of the bus will inevitably increase, which will cause trouble for the back-end wiring and cause crosstalk between lines.

(2) Clock synchronization problem

With the increase of integrated circuit frequency and the improvement of chip integration, global synchronization is becoming more and more difficult to achieve

(3) The problem of address space scalability. The increase of IP cores in the SoC system and the increase of interconnect lines will introduce more parasitic resistance and capacitance, resulting in increased circuit delay. The final delay may exceed the clock cycle, which actually limits The number of IP cores connected to the bus, thus limiting the scalability of the system

In recent years, most mapping algorithms use heuristic algorithms, including genetic algorithms, branch and bound algorithms, ant colony algorithms, simulated annealing algorithms, etc. cost, and it is easy to fall into a local optimal solution, it is difficult to apply to large-scale and fast IP core mapping, and it cannot guarantee to obtain low-energy mapping results in a short time

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