The invention belongs to the technical field of
electronics, in particular to a general
packing method for an FPGA (
field programmable gate array) configurable logical block (CLB). The method comprises the following steps: configuring and describing chips of the FPGA CLB as a series of directed simple graphs for constraining a satisfaction problem picture matching method; and then identifying a
logical function sub-circuit supported by the
chip from a user circuit by using the
constraint satisfaction problem picture matching method, and packing. According to the invention, only if a
library file which describes a target FPGA
logical function circuit is pre-defined, the FPGA chips of different structures, such as various functional configurations of a quick carry chain, a distribution type memory, a
shift register, an LUT5 (local user terminal 5), an LUT6 (local user terminal 6) and the like can be packed, thereby effectively improving the
utilization rate of the logical resources of the chips, and improving the
time sequence performance of the circuit. According to the invention, the circuit is optimized according to the appointed requirements, and the mapping of various modularized circuits is realized, thus the method has significant application in
system architecture designs and reconfigurable systems.