Distributed parallel minimum cost flow method and device for integrated circuit design

Abstract

The invention belongs to the field of integrated circuits and relates to a distributed parallel minimum cost flow method and a device for integrated circuit design. Since the method maintains a task queue for each processor to conduct distributed scheduling, the access conflict of task queues can be effectively reduced, and under the situation of more processor cores, better speedup ratio can be obtained. The device comprises an input unit, an output unit, a program storage unit, an external bus, an internal memory, a storage management unit, an input / output bridging unit, a system bus and a multi-core processor. Compared with a parallel minimum cost flow method which adopts central queue scheduling, the distributed parallel minimum cost flow method has the advantages that higher speedup ratio can be obtained. The method and the device can be used for the multi-core parallel realization of solutions to a broad class of integrated circuit design automation problems.

Description

technical field [0001] The invention belongs to the field of integrated circuits, and relates to a distributed parallel minimum cost flow method and device for integrated circuit design. Background technique [0002] As CMOS integrated circuit processes shrink, very large-scale integration (VLSI) design automation software is now using more and more computing resources to handle designs containing billions of transistors. At the same time, due to the limitations of power consumption and heat dissipation, the increase in the frequency of processors tends to stagnate and is replaced by multi-core processors. In the current commercial market, multi-core processors have become a mainstream product (1)-(2). In the field of integrated circuit design automation, how to use multi-core computer systems to improve the performance and efficiency of integrated circuit design has become a hot spot in international research (3)-(6). [0003] Many practical problems in integrated circuit...

AI Technical Summary

Problems solved by technology

[0004] In literature (13), a minimum cost flow method based on multi-core is proposed, but its parallel scheduling uses a central queue to store effective tasks. When there are more processor cores, the access conflict of the central queue will intensify, affecting parallelism. processing performance

Therefore, this method cannot be effectively accelerated with the number of processor cores, and the practicality of this method will decrease as the number of multi-cores increases in the future.

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